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Low-Power Electronics and Systems

Low-Power Electronics and Systems. Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849, USA http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu. Contents. Introduction Dynamic power

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Low-Power Electronics and Systems

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  1. Low-Power Electronics and Systems Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849, USA http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu Agrawal: VDAT'06 Tutorial II

  2. Contents • Introduction • Dynamic power • Short circuit power • Reduced supply voltage operation • Glitch elimination • Static (leakage) power reduction • Low power systems • State encoding • Processor and multi-core design • Books on low-power design Agrawal: VDAT'06 Tutorial II

  3. Introduction Power Consumption of VLSI Chips Why is it a concern? Agrawal: VDAT'06 Tutorial II

  4. ISSCC, Feb. 2001, Keynote “Ten years from now, microprocessors will run at 10GHz to 30GHz and be capable of processing 1 trillion operations per second -- about the same number of calculations that the world's fastest supercomputer can perform now. “Unfortunately, if nothing changes these chips will produce as much heat, for their proportional size, as a nuclear reactor. . . .” Patrick P. Gelsinger Senior Vice PresidentGeneral Manager Digital Enterprise Group INTEL CORP. Agrawal: VDAT'06 Tutorial II

  5. 10000 1000 Rocket Nozzle 100 Nuclear Power Density (W/cm2) Reactor 8086 10 4004 P6 8008 Pentium® 8085 386 286 486 8080 1 1970 1980 1990 2000 2010 Year VLSI Chip Power Density Source: Intel Sun’s Surface Hot Plate Agrawal: VDAT'06 Tutorial II

  6. Meaning of Low-Power Design • Design practices that reduce power consumption at least by one order of magnitude; in practice 50% reduction is often acceptable. • General considerations in low-power design • Algorithms and architectures • High-level and software techniques • Gate and circuit-level methods • Power estimation techniques • Test power Agrawal: VDAT'06 Tutorial II

  7. Topics in Low-Power • Power dissipation in CMOS circuits • Device technology • Low-power CMOS technologies • Energy recovery methods • Circuit and gate level methods • Logic synthesis • Dynamic power reduction techniques • Leakage power reduction • System level methods • Microprocessors • Arithmetic circuits • Low power memory technology • Test power • Power estimation methods and tools Agrawal: VDAT'06 Tutorial II

  8. Power in a CMOS Gate VDD iDD(t) Ground Agrawal: VDAT'06 Tutorial II

  9. Power Dissipation in CMOS Logic (0.25µ) Ptotal (0→1) = CL VDD2 + tscVDD Ipeak+VDDIleakage VDD VDD CL %75 %20 %5 Agrawal: VDAT'06 Tutorial II

  10. Power and Energy • Instantaneous power (Watts) P(t) = iDD(t) VDD • Peak power (Watts) Ppeak = Max {P(t)} • Average power (Watts) Pav = [ ∫0TP(t) dt ]/T • Energy (Joules) E = ∫0TP(t) dt Agrawal: VDAT'06 Tutorial II

  11. Low-Power Design Techniques • Circuit and gate level methods • Reduced supply voltage • Adiabatic switching and charge recovery • Logic design for reduced activity • Reduced Glitches • Transistor sizing • Pass-transistor logic • Pseudo-nMOS logic • Multi-threshold gates Agrawal: VDAT'06 Tutorial II

  12. Low-Power Design Techniques • Functional and architectural methods • Clock suppression • Clock frequency reduction • Supply voltage reduction • Power down • Algorithmic and Software methods Agrawal: VDAT'06 Tutorial II

  13. Test Power • Power grid on a VLSI chip is designed for certain current capacity during functional operation: • Average current → heat dissipation • Peak current → noise, ground bounce • Problem – Tests like scan or BIST are nonfunctional and may cause higher than the functional circuit activity; a functionally good chip can fail the test. Agrawal: VDAT'06 Tutorial II

  14. Power Estimation Methods • Spice: Accurate but expensive • Logic-level • Event-driven simulation • Statistical • Probabilistic • High-level: Hierarchical Agrawal: VDAT'06 Tutorial II

  15. Components of Power • Dynamic • Signal transitions • Logic activity • Glitches • Short-circuit • Static • Leakage Ptotal = Pdyn + Pstat = Ptran + Psc + Pstat Agrawal: VDAT'06 Tutorial II

  16. Power of a Transition: Ptran VDD Ron ic(t) vi (t) vo(t) CL R=large Ground Agrawal: VDAT'06 Tutorial II

  17. Charging of a Capacitor R t = 0 v(t) i(t) C V Charge on capacitor, q(t) = C v(t) Current, i(t) = dq(t)/dt = C dv(t)/dt Agrawal: VDAT'06 Tutorial II

  18. i(t) = C dv(t)/dt = [V – v(t)] /R dv(t) V – v(t) ─── = ───── dt RC dv(t) dt ∫ ───── = ∫───── V – v(t) RC -t ln [V – v(t)] = ── + A RC Initial condition, t = 0, v(t) = 0 → A = ln V -t v(t) = V [1 – exp(───)] RC Agrawal: VDAT'06 Tutorial II

  19. -t v(t) = V [1 – exp( ── )] RC dv(t) V -t i(t) = C ─── = ── exp( ── ) dt R RC Agrawal: VDAT'06 Tutorial II

  20. Total Energy Per Charging Transition from Power Supply ∞∞ V2 -t Etrans = ∫ V i(t) dt = ∫ ── exp( ── ) dt 00 R RC = CV2 Agrawal: VDAT'06 Tutorial II

  21. Energy Dissipated per Transition in Resistance (R) of “On” Transistors ∞ V2∞ -2t R ∫ i2(t) dt = R ── ∫ exp( ── ) dt 0 R20 RC 1 = ─ CV2 2 Agrawal: VDAT'06 Tutorial II

  22. Energy Stored in Charged Capacitor ∞ ∞ -t V -t ∫ v(t) i(t) dt = ∫ V [1- exp( ── )]─ exp( ── ) dt 00 RC R RC 1 = ─ CV2 2 Agrawal: VDAT'06 Tutorial II

  23. Transition Power • Gate output rising transition • Energy dissipated in pMOS transistor = CV2/2 • Energy stored in capacitor = CV2/2 • Gate output falling transition • Energy dissipated in nMOS transistor = CV2/2 • Energy dissipated per transition = CV2/2 • Power dissipation: Ptrans = Etransα fck = α fck CV2/2 α = activity factor Agrawal: VDAT'06 Tutorial II

  24. Short Circuit Current, isc(t) VDD VDD VDD - VTp Vi(t) Vi(t) Vo(t) Vo(t) Volt GND VTn 0 Iscmaxf isc(t) Amp Time (ns) tB tE 1 0 Agrawal: VDAT'06 Tutorial II

  25. Short-Circuit Energy per Transition • Escf =∫tBtE VDD isc(t)dt = (tE – tB) IscmaxfVDD /2 • Escf = tf (VDD- |VTp|-VTn) Iscmaxf /2 • Escr = tr (VDD- |VTp| -VTn) Iscmaxr /2 • Escf = 0, when VDD = |VTp| + VTn Agrawal: VDAT'06 Tutorial II

  26. Short-Circuit Power and Voltage Scaling • Decreases and eventually becomes zero when VDD is scaled down but the threshold voltages are not scaled down. • References: • M. A. Ortega and J. Figueras, “Short Circuit Power Modeling in Submicron CMOS,” PATMOS’96, Aug. 1996, pp. 147-166. • T. Sakurai and A. Newton, “Alpha-power Law MOSFET model and Its Application to a CMOS Inverter,” IEEE J. Solid State Circuits, vol. 25, April 1990, pp. 584-594. Agrawal: VDAT'06 Tutorial II

  27. Psc and Output Capacitance VDD Ron ic(t)+isc(t) vi (t) vo(t) CL tr tf R=large vo(t) ─── R↑ Ground Agrawal: VDAT'06 Tutorial II

  28. isc and Output Capacitance -t VDD[1- exp(─────)] vo(t) R↓tf (t)C Isc(t) = ──── = ────────────── R↑tf (t) R↑tf (t) Agrawal: VDAT'06 Tutorial II

  29. iscmax and Output Capacitance i Small C Large C vo(t) vo(t) iscmax 1 ──── R↑tf (t) t tf Agrawal: VDAT'06 Tutorial II

  30. Psc, Output Rise Times, Capacitance • For given input rise and fall times short circuit power decreases as output capacitance increases. • Short circuit power increases with increase of input rise and fall times. • Short circuit power is reduced if output rise and fall times are smaller than the input rise and fall times. Agrawal: VDAT'06 Tutorial II

  31. Effects of Scaling Down • 1-16% short-circuit power at 0.7 micron • 4-37% at 0.35 micron • 12-60% at 0.17 micron • Reference: S. R. Vemuru and N. Steinberg, “Short Circuit Power Dissipation Estimation for CMOS Logic Gates,” IEEE Trans. on Circuits and Systems I, vol. 41, Nov. 1994, pp. 762-765. Agrawal: VDAT'06 Tutorial II

  32. Summary: Short-Circuit Power • Short-circuit power is consumed by each transition (increases with input transition time). • Reduction requires that gate output transition should not be faster than the input transition (faster gates can consume more short-circuit power). • Increasing the output load capacitance reduces short-circuit power. • Scaling down of supply voltage with respect to threshold voltages reduces short-circuit power. Agrawal: VDAT'06 Tutorial II

  33. Dynamic Power isc VDD Dynamic Power = CLVDD2/2 + Psc R Vo Vi CL R Ground Agrawal: VDAT'06 Tutorial II

  34. Dynamic Power Reduction • Reduce power per transition • Reduced voltage operation – voltage scaling • Capacitance minimization – device sizing • Reduce number of transitions • Glitch elimination Agrawal: VDAT'06 Tutorial II

  35. CMOS Dynamic Power Dynamic Power = Σ 0.5 αifclk CLiVDD2 All gates i ≈ 0.5 αfclk CLVDD2 ≈ α01fclk CLVDD2 where α average gate activity factor α01 = 0.5α, average 0→1 trans. fclk clock frequency CL total load capacitance VDD supply voltage Agrawal: VDAT'06 Tutorial II

  36. Example: 0.25μm CMOS Chip • f = 500MHz • Average capacitance = 15fF/gate • VDD = 2.5V • 106 gates • Power = α01f CLVDD2 = α01×500×106×(15×10-15×106) ×2.52 = 46.9W, for α01 = 1.0 Agrawal: VDAT'06 Tutorial II

  37. Signal Activity, α T=1/f Clock α01= 1.0 α01= 0.5 Comb. signals α01= 0.5 Agrawal: VDAT'06 Tutorial II

  38. Reducing Dynamic Power • Dynamic power reduction is • Quadratic with reduction of supply voltage • Linear with reduction of capacitance Agrawal: VDAT'06 Tutorial II

  39. 0.25μm CMOS Inverter, VDD=2.5V 2.5 2.0 1.5 1.0 0.5 0 0 -4 -8 -12 -16 -20 Gain Vout(V) 0 0.5 1.0 1.5 2.0 2.5 0 0.5 1.0 1.5 2.0 2.5 Vin (V) Vin (V) Agrawal: VDAT'06 Tutorial II

  40. 0.25μm CMOS Inverter, VDD< 2.5V 2.5 2.0 1.5 1.0 0.5 0 0.2 0.15 0.1 0.05 0 Vout (V) Vout(V) 0 0.5 1.0 1.5 2.0 2.5 0 0.05 0.1 0.15 0.2 Gain = -1 Vin (V) Vin (V) Agrawal: VDAT'06 Tutorial II

  41. Lower Bound on VDD • For proper operation of gate, maximum gain (for Vin = VDD/2) should be greater than 1. • Gainmax = -(1/n)[exp(VDD /2ΦT) – 1] = -1 • n = 1.5 • ΦT = kT/q = 26mV • VDD = 48V • VDDmin > 2 to 4 times kT/q or ~100mV at room temperature (27oC) • Ref.: J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Upper Saddle River, New Jersey: Pearson Education, 2003. Agrawal: VDAT'06 Tutorial II

  42. Impact of VDD on Performance CLVDD Inverter delay = K ─────── (VDD – Vt )α 40 30 20 10 0 Delay (ns) Power (log scale) Power Delay 0.6V 1.8V 3.0V VDD VDD=Vt Agrawal: VDAT'06 Tutorial II

  43. Optimum Power × Delay VDD3 Power × Delay, PD = constant × ─────── (VDD – Vt)α For minimum power-delay product, d(PD)/dVDD = 0 3Vt VDD = ─── 3 – α For long channel devices, α = 2, VDD = 3Vt For very short channel devices, α = 1, VDD = 1.5Vt Agrawal: VDAT'06 Tutorial II

  44. Transistor Sizing for Performance • Problem: If we increase W/L to make the charging or discharging of load capacitance, then the increased W increases the load for the driving gate Cin CL Agrawal: VDAT'06 Tutorial II

  45. Fixed-Taper Buffer Delay = t0 αn-1 αi-1 α2 α 1 Vout Vin Cin CL Ci= αi-1Cin CL = αnCin Ref.: J. Segura and C. F. Hawkins, CMOS Electronics, How It Works, How It Fails, Piscataway, New Jersey: IEEE Press, 2004. Agrawal: VDAT'06 Tutorial II

  46. Buffer (Cont.) αn= CL/Cin ln (CL/Cin) n = ────── ln α ith stage delay, ti = αt0, i = 1, . . . n, because each stage drives a stage α times bigger than itself. Agrawal: VDAT'06 Tutorial II

  47. Buffer (Cont.) n Total delay = Σti = nαt0 i=1 = ln(CL/Cin) αt0/ln(α) Agrawal: VDAT'06 Tutorial II

  48. Buffer (Cont.) Differentiating total delay with respect to α and equating to 0, we get αopt = e ≈ 2.7 The optimum number of stages is nopt = ln(CL/Cin) Agrawal: VDAT'06 Tutorial II

  49. Further Reading B. S. Cherkauer and E. G. Friedman, “A Unified Design Methodology for CMOS Tapered Buffers,” IEEE Trans. VLSI Systems, vol. 3, no. 1, pp. 99-111, March 1995. Agrawal: VDAT'06 Tutorial II

  50. Logic Activity and Glitches 1 6 2 5 4 3 d=1 d=1 d=2 7 d=1 Agrawal: VDAT'06 Tutorial II

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