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  1. ECE 545 Digital System Design with VHDL Course web page: ECE web page  Courses  Course web pages  ECE 545 http://ece.gmu.edu/coursewebpages/ECE/ECE545/F11/

  2. Kris Gaj • Research and teaching interests: • reconfigurable computing • computer arithmetic • cryptography • network security • Contact: • The Engineering Building, room 3225 • kgaj@gmu.edu Office hours: Thursday, 7:30-8:30 PM, Tuesday, 7:30-8:30 PM, and by appointment

  3. ECE 545 Part of: MS in Computer Engineering One of five core courses (must be passed with B or better) Fundamental course for the specialization area: Digital Systems Design Elective course in the remaining specialization areas MS in Electrical Engineering Elective

  4. ECE 545 Part of: PhD in Electrical and Computer Engineering Knowledge tested at the Technical Qualifying Exam (TQE) Topic 2: Digital Design and Computer Organization

  5. Recommended program & specialization I am interested in… I want to specialize primarily in… CAD tools & Design Automation Hardware Description Languages FPGAs & Reconfigurable computing Computer Arithmetic Front-end ASICDesign (algorithmic downto gate level) Back-end ASICDesign (circuit and mask layout levels) Analog & Digital Circuit Design VLSI Fabrication Microelectronics Nanoelectronics Semiconductor Devices MS CpE Digital Systems Design VLSI Digital Systems Design ASICs & FPGAs VHDL/Verilog CAD Tools Reconfigurable Computing Microelectronics VLSI Fabrication Nanoelectronics MS EE Microelectronics/ Nanoelectronics

  6. Courses Design level Computer Arithmetic VLSI Design for ASICs VLSI Test Concepts Digital System Design with VHDL algorithmic ECE 645 ECE 545 register-transfer ECE 682 ECE 681 gate ECE 586 Digital Integrated Circuits transistor ECE 680 PhysicalVLSI Design layout Semiconductor Device Fundamentals MOS Device Electronics ECE 584 ECE684 devices

  7. CpE CpE Microprocessors and Embedded Systems Digital Systems Design ECE 545 Digital System Design with VHDL ECE 586 Digital Integrated Circuits ECE 645 Computer Arithmetic ECE 681 VLSI Design for ASICs ECE 682 VLSI Test Concepts ECE 510 Real-Time Concepts ECE 511 Microprocessors ECE 611 Advanced Microprocessors ECE 612 Real-Time Embedded Systems ECE 641 Computer System Architecture Pre- Approved Electives CS 540, 583 (languages, algorithms) CS 635 (parallel machines) ECE 542, 642, 742 (networks) ECE 645, 681 (digital design) ECE 548 (sequential mach. theory) Suggested Electives ECE 584, 684, … (technology) ECE 511, 611, … (microprocessors) ECE 646, 746, … (applications) K. Gaj, K. Hintz, H. Homayoun, J. Kaps, T. Storey H. Homayoun, J. Kaps, P. Pachowicz, C. Sabzevari Professors

  8. DIGITAL SYSTEMS DESIGN • Concentration advisors:Kris Gaj, Jens-Peter Kaps, Ken Hintz • ECE 545 Digital System Design with VHDL– K. Gaj, project, FPGA design with VHDL, • Aldec/Mentor Graphics, Xilinx/Altera • 2. ECE 645 Computer Arithmetic– K. Gaj, project, FPGA design with VHDL • Aldec/Mentor Graphics, Xilinx/Altera • 3. ECE 681 VLSI Design for ASICs– H. Homayoun, project/lab, front-end and back-end ASIC design with Synopsys tools • 4. ECE 586 Digital Integrated Circuits – D. Ioannou, R. Mulpuri, • 5. ECE 682 VLSI Test Concepts • – T. Storey

  9. Grading Scheme • Homework - 10% • Project - 40% • Midterm Exam - 20% • Final Exam - 30%

  10. Midterm exam 1 • 2 hours 30 minutes • in class • design-oriented • open-books, open-notes • practice exams available on the web Tentative date: Last week of October

  11. Final exam • 2 hours 45 minutes • in class • design-oriented • open-books, open-notes • practice exams available on the web Date: Thursday, December 13, 4:30-7:15pm

  12. Textbooks

  13. Required Textbook Pong P. Chu, RTL Hardware Design Using VHDL, Wiley-Interscience, 2006.

  14. Supplementary Textbook – Basics Refresher Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, McGraw-Hill, 3rd or 2nd Edition

  15. Supplementary Textbook – Advanced Hubert Kaeslin, Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication, Cambridge University Press; 1st Edition, 2008. Used in ECE 681 “VLSI Design for ASICs”

  16. Technology & Tools

  17. Block RAMs Block RAMs What is an FPGA? Configurable Logic Blocks I/O Blocks Block RAMs

  18. FPGA Design process (1) Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds….. Specification / Pseudocode On-paper hardware design (Block diagram & ASM chart) VHDL description (Your Source Files) Library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31downto0); data_output: out std_logic_vector(31downto0); out_full: in std_logic; key_input: in std_logic_vector(31downto0); key_read: out std_logic; ); end AES_core; Functional simulation Synthesis Post-synthesis simulation

  19. FPGA Design process (2) Implementation Timing simulation Configuration On chip testing

  20. Simulation Tools

  21. FPGA Synthesis Tools

  22. Logic Synthesis VHDL description Circuit netlist architecture MLU_DATAFLOW of MLU is signal A1:STD_LOGIC; signal B1:STD_LOGIC; signal Y1:STD_LOGIC; signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC; begin A1<=A when (NEG_A='0') else not A; B1<=B when (NEG_B='0') else not B; Y<=Y1 when (NEG_Y='0') else not Y1; MUX_0<=A1 and B1; MUX_1<=A1 or B1; MUX_2<=A1 xor B1; MUX_3<=A1 xnor B1; with (L1 & L0) select Y1<=MUX_0 when "00", MUX_1 when "01", MUX_2 when "10", MUX_3 when others; end MLU_DATAFLOW;

  23. After synthesis the entire implementation process is performed by FPGA vendor tools FPGA Implementation

  24. Design Process control from Active-HDL

  25. Xilinx FPGA Tools ECE Labs Aldec Active-HDL Design Flow Xilinx ISE Design Flow Aldec Active-HDL (IDE) Mentor Graphics ModelSim SE Xilinx XST & Synopsys Synplify Premier Xilinx ISE Design Suite Xilinx XST & Synopsys Synplify Premier Xilinx ISE Design Suite (IDE) simulation synthesis implementation

  26. Xilinx FPGA Tools Home Xilinx ISE Design Flow Aldec Active-HDL Design Flow Mentor Graphics ModelSim PE Student Edition Aldec Active-HDL Student Edition (IDE) Xilinx XST (restricted) Xilinx XST (restricted) Xilinx ISE WebPACK (restricted) Xilinx ISE WebPACK (IDE) (restricted) simulation synthesis implementation

  27. Altera FPGA Tools ECE Labs Altera Design Flow Mentor Graphics ModelSim-Altera Altera Quartus II Subscription Edition simulation synthesis & implementation

  28. Altera FPGA Tools Home Altera Design Flow Mentor Graphics ModelSim-Altera Starter (restricted) Altera Quartus II Web Edition (restricted) simulation synthesis & implementation

  29. Project

  30. Project • semester-long • related to the research project conducted by • Cryptographic Engineering Research Group (CERG) • at GMU • supporting NIST (National Institute of Standards • and Technology) in the evaluation of candidates • for a new cryptographic standard

  31. Background

  32. Crypto 101

  33. Cryptography is Everywhere Buying a book on-line Withdrawing cash from ATM Backing up files on remote server Teleconferencing over Intranets

  34. Cryptographic Standards Before 1997 Secret-Key Block Ciphers 2005 1999 1977 IBM & NSA DES – Data Encryption Standard Triple DES 1995 2003 1993 Hash Functions NSA SHA-1–Secure Hash Algorithm SHA-2 SHA 2000 1970 1990 1980 2010 time

  35. Why a Contest for a Cryptographic Standard? • Avoid back-door theories • Speed-up the acceptance of the standard • Stimulate non-classified research on methods of • designing a specific cryptographic transformation • Focus the effort of a relatively small cryptographic • community

  36. Cryptographic Standard Contests IX.1997 X.2000 AES 15 block ciphers 1 winner NESSIE I.2000 XII.2002 CRYPTREC V.2008 XI.2004 34 stream ciphers 4 HW winners + 4 SW winners eSTREAM XII.2012 X.2007 51 hash functions 1 winner SHA-3 96 97 98 99 00 01 02 03 04 05 06 07 08 09 10 11 12 13 time

  37. Cryptographic Contests - Evaluation Criteria Security Software Efficiency Hardware Efficiency μProcessors μControllers FPGAs ASICs Licensing Simplicity Flexibility

  38. Specific Challenges of Evaluations in Cryptographic Contests • Very wide range of possible applications, and as a result • performance and cost targets • throughput: single Mbits/s to hundreds Gbits/s • cost: single cents to thousands of dollars • Winner in use for the next 20-30 years, implemented using • technologies not in existence today • Large number of candidates • Limited time for evaluation • Only one winner and the results are final

  39. Mitigating Circumstances • Security is a primary criterion • Performance of competing algorithms tend to very significantly • (sometimes as much as 500 times) • Only relatively large differences in performance matter • (typically at least 20%) • Multiple groups independently implement the same algorithms • (catching mistakes, comparing best results, etc.) • Second best may be good enough

  40. AES Contest 1997-2000

  41. Rules of the Contest Each team submits Detailed cipher specification Justification of design decisions Tentative results of cryptanalysis Source code in C Source code in Java Test vectors

  42. AES: Candidate Algorithms 2 8 4 Germany: Korea: Canada: CAST-256 Deal Magenta Crypton Japan: Belgium: USA: E2 Mars RC6 Twofish Safer+ HPC Rijndael France: 1 DFC Israel, UK, Norway: Australia: Costa Rica: LOKI97 Serpent Frog

  43. AES Contest Timeline June 1998 Round 1 15 Candidates CAST-256, Crypton, Deal, DFC, E2, Frog, HPC, LOKI97, Magenta, Mars, RC6, Rijndael, Safer+, Serpent, Twofish, Security Software efficiency August 1999 Round 2 5 final candidates Mars, RC6, Twofish (USA) Rijndael, Serpent (Europe) Security Software efficiency Hardware efficiency October 2000 1 winner: Rijndael Belgium

  44. NIST Report: Security & Simplicity Security MARS High Serpent Twofish Rijndael Adequate RC6 Simple Complex Simplicity

  45. Efficiency in software: NIST-specified platform 200 MHz Pentium Pro, Borland C++ Throughput [Mbits/s] 128-bit key 192-bit key 256-bit key 30 25 20 15 10 5 0 Rijndael Twofish RC6 Mars Serpent

  46. NIST Report: Software Efficiency Encryption and Decryption Speed 32-bit processors 64-bit processors DSPs Rijndael Twofish RC6 Rijndael Twofish high Rijndael Mars Twofish Mars RC6 Mars RC6 medium low Serpent Serpent Serpent

  47. Efficiency in FPGAs: Speed Xilinx Virtex XCV-1000 Throughput [Mbit/s] 500 444 George Mason University 431 450 414 University of Southern California 400 353 Worcester Polytechnic Institute 350 294 300 250 177 200 173 149 143 150 112 102 104 88 100 62 61 50 0 RC6 Mars Rijndael Twofish Serpent x1 Serpent x8