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Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic

ECE 448 Lecture 3. Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic. R eading. Required. P. Chu, FPGA Prototyping by VHDL Examples Chapter 3, RT-level combinational circuit. Recommended.

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Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic

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  1. ECE 448 Lecture 3 Combinational-Circuit Building BlocksData Flow Modeling of Combinational Logic ECE 448 – FPGA and ASIC Design with VHDL

  2. Reading Required • P. Chu, FPGA Prototyping by VHDL Examples • Chapter 3, RT-level combinational circuit Recommended • S. Brown and Z. Vranesic,Fundamentals of Digital Logic with VHDL Design • Chapter 6, Combinational-Circuit Building Blocks • Chapter 5.5, Design of Arithmetic Circuits Using • CAD Tools ECE 448 – FPGA and ASIC Design with VHDL

  3. VHDL Design Styles ECE 448 – FPGA and ASIC Design with VHDL

  4. VHDL Design Styles dataflow VHDL Design Styles • Testbenches behavioral(sequential) structural Components and interconnects Concurrent statements Sequential statements • Registers • State machines • Instruction decoders Subset most suitable for synthesis ECE 448 – FPGA and ASIC Design with VHDL

  5. Synthesizable VHDL Dataflow VHDL Design Style VHDL code synthesizable Dataflow VHDL Design Style VHDL code synthesizable ECE 448 – FPGA and ASIC Design with VHDL

  6. Data-Flow VHDL Concurrent Statements • concurrent signal assignment () • conditional concurrent signal assignment • (when-else) • selected concurrent signal assignment • (with-select-when) • generate scheme for equations • (for-generate) ECE 448 – FPGA and ASIC Design with VHDL

  7. Modeling Wires and Buses ECE 448 – FPGA and ASIC Design with VHDL

  8. Signals SIGNALa : STD_LOGIC; SIGNALb : STD_LOGIC_VECTOR(7 DOWNTO 0); a 1 wire b bus 8 ECE 448 – FPGA and ASIC Design with VHDL

  9. Merging wires and buses a 4 10 d b 5 c SIGNALa: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNALb: STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNALc: STD_LOGIC; SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0); d <= a & b & c; ECE 448 – FPGA and ASIC Design with VHDL

  10. Splitting buses a 4 10 d b 5 c SIGNALa: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNALb: STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNALc: STD_LOGIC; SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0); a <= d(9 downto 6); b <= d(5 downto 1); c <= d(0); ECE 448 – FPGA and ASIC Design with VHDL

  11. Combinational-Circuit Building Blocks ECE 448 – FPGA and ASIC Design with VHDL

  12. Fixed Shifters & Rotators ECE 448 – FPGA and ASIC Design with VHDL

  13. Fixed Shift in VHDL A(1) A(0) SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL AshiftR: STD_LOGIC_VECTOR(3 DOWNTO 0); A(3) A(2) A A>>1 AshiftR ‘0’ A(3) A(2) A(1) AshiftR <= ECE 448 – FPGA and ASIC Design with VHDL

  14. Fixed Rotation in VHDL SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL ArotL: STD_LOGIC_VECTOR(3 DOWNTO 0); A(3) A(2) A(1) A(0) A A<<<1 ArotL A(2) A(1) A(0) A(3) ArotL <= ECE 448 – FPGA and ASIC Design with VHDL

  15. Gates ECE 448 – FPGA and ASIC Design with VHDL

  16. x 1 x 2 x 1 × × ¼ × x x x × x x 1 2 n 1 2 x 2 x n (a) AND gates x 1 x 2 x 1 ¼ x + x x + x + + x 1 2 1 2 n x 2 x n (b) OR gates x x (c) NOT gate Basic Gates – AND, OR, NOT ECE 448 – FPGA and ASIC Design with VHDL

  17. Basic Gates – NAND, NOR ECE 448 – FPGA and ASIC Design with VHDL

  18. DeMorgan’s Theorem and other symbols for NAND, NOR x 1 x x 1 1 x x 2 2 x 2 x x x x = + (a) 1 2 1 2 x 1 x x 1 1 x x 2 2 x 2 x x x x + = (b) 1 2 1 2 ECE 448 – FPGA and ASIC Design with VHDL

  19. Å x x f = x x 1 2 1 2 0 0 0 0 1 1 x 1 1 0 1 Å f = x x x 1 2 2 1 1 0 (a) Truth table (b) Graphical symbol x 1 x 2 Å f = x x 1 2 (c) Sum-of-products implementation Basic Gates – XOR ECE 448 – FPGA and ASIC Design with VHDL

  20. Basic Gates – XNOR Å x x f = x x 1 2 1 2 0 0 1 0 1 0 x 1 . 1 0 0 Å f = x x = x x x 1 2 1 2 2 1 1 1 (a) Truth table (b) Graphical symbol x 1 x 2 Å f = x x 1 2 (c) Sum-of-products implementation ECE 448 – FPGA and ASIC Design with VHDL

  21. Data-flow VHDL: Example x y s cin cout ECE 448 – FPGA and ASIC Design with VHDL

  22. Data-flow VHDL: Example (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY fulladd IS PORT (x : IN STD_LOGIC ; y: IN STD_LOGIC ; cin : IN STD_LOGIC ; s : OUT STD_LOGIC ; cout : OUT STD_LOGIC ) ; END fulladd ; ECE 448 – FPGA and ASIC Design with VHDL

  23. Data-flow VHDL: Example (2) ARCHITECTURE dataflow OF fulladd IS BEGIN s <= x XOR y XOR cin ; cout <= (x AND y) OR (cin AND x) OR (cin AND y) ; END dataflow ; ECE 448 – FPGA and ASIC Design with VHDL

  24. Logic Operators • Logic operators • Logic operators precedence and or nand nor xor not xnor only in VHDL-93 Highest not and or nand nor xor xnor Lowest ECE 448 – FPGA and ASIC Design with VHDL

  25. No Implied Precedence Wanted: y = ab + cd Incorrect y <= a and b or c and d ; equivalent to y <= ((a and b) or c) and d ; equivalent to y = (ab + c)d Correct y <= (a and b) or (c and d) ; ECE 448 – FPGA and ASIC Design with VHDL

  26. Multiplexers ECE 448 – FPGA and ASIC Design with VHDL

  27. 2-to-1 Multiplexer s w 0 0 f w 1 1 f s w 0 0 w 1 1 (b) Truth table (a) Graphical symbol ECE 448 – FPGA and ASIC Design with VHDL

  28. VHDL code for a 2-to-1 Multiplexer LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1 IS PORT ( w0, w1, s : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END mux2to1 ; ARCHITECTURE dataflow OF mux2to1 IS BEGIN f <= w0 WHEN s = '0' ELSE w1 ; END dataflow ; ECE 448 – FPGA and ASIC Design with VHDL

  29. Cascade of twomultiplexers w 0 3 0 w 1 y w 2 1 1 s2 s1 ECE 448 – FPGA and ASIC Design with VHDL

  30. VHDL code for a cascade of two multiplexers LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux_cascade IS PORT ( w1, w2, w3: IN STD_LOGIC ; s1, s2 : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END mux_cascade ; ARCHITECTURE dataflow OF mux2to1 IS BEGIN f <= w1 WHEN s1 = ‘1' ELSE w2 WHEN s2 = ‘1’ ELSE w3 ; END dataflow ; ECE 448 – FPGA and ASIC Design with VHDL

  31. Operators • Relational operators • Logic and relational operators precedence = /= < <= > >= Highest not = /= < <= > >= and or nand nor xor xnor Lowest ECE 448 – FPGA and ASIC Design with VHDL

  32. Priority of logic and relational operators compare a = bc Incorrect … when a = b and c else … equivalent to … when (a = b) and c else … Correct … when a = (b and c) else … ECE 448 – FPGA and ASIC Design with VHDL

  33. VHDL operators ECE 448 – FPGA and ASIC Design with VHDL

  34. 4-to-1 Multiplexer s 0 s s s f 1 1 0 w w 00 0 0 0 0 w 01 w 1 0 1 f 1 w 10 w 2 1 0 2 w 11 3 w 1 1 3 (a) Graphic symbol (b) Truth table ECE 448 – FPGA and ASIC Design with VHDL

  35. VHDL code for a 4-to-1 Multiplexer LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux4to1 IS PORT ( w0, w1, w2, w3 : IN STD_LOGIC ; s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END mux4to1 ; ARCHITECTURE dataflow OF mux4to1 IS BEGIN WITH s SELECT f <= w0 WHEN "00", w1 WHEN "01", w2 WHEN "10", w3 WHEN OTHERS ; END dataflow ; ECE 448 – FPGA and ASIC Design with VHDL

  36. Decoders ECE 448 – FPGA and ASIC Design with VHDL

  37. 2-to-4 Decoder w w y y y y En 1 0 3 2 1 0 w y 1 3 1 0 0 0 0 0 1 w y 0 2 0 1 0 0 1 0 1 y 1 1 1 0 0 1 0 0 y En 0 1 1 1 1 0 0 0 x x 0 0 0 0 0 (a) Truth table (b) Graphical symbol ECE 448 – FPGA and ASIC Design with VHDL

  38. VHDL code for a 2-to-4 Decoder LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY dec2to4 IS PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END dec2to4 ; ARCHITECTURE dataflow OF dec2to4 IS SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ; BEGIN Enw <= En & w ; WITH Enw SELECT y <= “0001" WHEN "100", "0010" WHEN "101", "0100" WHEN "110", “1000" WHEN "111", "0000" WHEN OTHERS ; END dataflow ; ECE 448 – FPGA and ASIC Design with VHDL

  39. Adders ECE 448 – FPGA and ASIC Design with VHDL

  40. 16-bit Unsigned Adder 16 16 X Y Cout Cin S 16 ECE 448 – FPGA and ASIC Design with VHDL

  41. Operations on Unsigned Numbers For operations on unsigned numbers USE ieee.numeric_std.all and signals of the type UNSIGNED and conversion functions: std_logic_vector(), unsigned() OR USE ieee.std_logic_unsigned.all and signals of the type STD_LOGIC_VECTOR (recommended) (permitted) ECE 448 – FPGA and ASIC Design with VHDL

  42. VHDL code for a 16-bit Unsigned Adder LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY adder16 IS PORT ( Cin : IN STD_LOGIC ; X : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ; Cout : OUT STD_LOGIC ) ; END adder16 ; ARCHITECTURE dataflow OF adder16 IS SIGNAL Sum : STD_LOGIC_VECTOR(16 DOWNTO 0) ; BEGIN Sum <= ('0' & X) + Y + Cin ; S <= Sum(15 DOWNTO 0) ; Cout <= Sum(16) ; END dataflow ; ECE 448 – FPGA and ASIC Design with VHDL

  43. Addition of Unsigned Numbers (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.numeric_std.all ; ENTITY adder16 IS PORT ( Cin : IN STD_LOGIC ; X : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ; Cout : OUT STD_LOGIC ) ; END adder16 ; ECE 448 – FPGA and ASIC Design with VHDL

  44. Addition of Unsigned Numbers (2) ARCHITECTURE dataflow OF adder16 IS SIGNAL Xu : UNSIGNED(16 DOWNTO 0); SIGNAL Yu : UNSIGNED(15 DOWNTO 0); SIGNAL Su : UNSIGNED(16 DOWNTO 0) ; SIGNAL Cinu : UNSIGNED(1 DOWNTO 0); BEGIN Xu <= unsigned(‘0’ & X); Yu <= unsigned(Y); Cinu <= unsigned(‘0’ & Cin); Su <= Xu + Yu + Cinu ; S <= std_logic_vector(Su(15 DOWNTO 0)) ; Cout <= Su(16) ; END dataflow; ECE 448 – FPGA and ASIC Design with VHDL

  45. Operations on Signed Numbers For operations on signed numbers USE ieee.numeric_std.all, signals of the type SIGNED, and conversion functions: std_logic_vector(), signed() OR USE ieee.std_logic_signed.all and signals of the type STD_LOGIC_VECTOR (recommended) (permitted) ECE 448 – FPGA and ASIC Design with VHDL

  46. Signed and Unsigned Types Behave exactly like STD_LOGIC_VECTOR plus, they determine whether a given vector should be treated as a signed or unsigned number. Require USE ieee.numeric_std.all; ECE 448 – FPGA and ASIC Design with VHDL

  47. Multipliers ECE 448 – FPGA and ASIC Design with VHDL

  48. Unsigned vs. Signed Multiplication Unsigned Signed 1111 1111 1111 1111 15 15 -1 -1 x x x x 11100001 225 00000001 1 ECE 448 – FPGA and ASIC Design with VHDL

  49. 8x8-bit Unsigned Multiplier 8 8 a b c 16 ECE 448 – FPGA and ASIC Design with VHDL

  50. Multiplication of unsigned numbers LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all ; entity multiply is port( a : in STD_LOGIC_VECTOR(7 downto 0); b : in STD_LOGIC_VECTOR(7 downto 0); c : out STD_LOGIC_VECTOR(15 downto 0) ); end multiply; architecture dataflow of multiply is c <= a * b; end dataflow; ECE 448 – FPGA and ASIC Design with VHDL

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