Combinational Logic

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Combinational Logic - PowerPoint PPT Presentation

Chapter 4. Combinational Logic. 4.1 Introduction. Logic circuits for digital systems may be. . combinational or sequential. A combinational circuit consists of logic gates. . whose outputs at any time are determined. from only the present combination of inputs. 2.

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Chapter 4

Combinational Logic

4.1 Introduction

Logic circuits for digital systems may be

combinational or sequential.

A combinational circuit consists of logic gates

whose outputs at any time are determined

from only the present combination of inputs.

2

4.2 Combinational Circuits

Logic circuits for digital system

Sequential circuits

contain memory elements

the outputs are a function of the current inputs and the

state of the memory elements

the outputs also depend on past inputs

3

A combinational circuits

n

2 possible combinations of input values

Combinational circuits

n input m output

Combinatixnal

variables variables

xoxic Circuit

Specific functions

and multiplexers

4

4-3 Analysis Procedure

A combinational circuit

make sure that it is combinational not sequential

No feedback path

derive its Boolean functions (truth table)

design verification

A straight-forward procedure

F

= AB+AC+BC

2

T

= A+B+C

= AxB+C

1

1

T

= ABC

2

T

= F2'T1

3

F

= T3+T2

1

6

F

= T

+T

= F

'T

+ABC

1 3 2 2 1

= (AB+AC+BC)'(A+B+C)+ABC

= (A'+B')(A'+C“)(B'+C')(A+B+C)+ABC

= (A'+B'C')(AB'+AC'+BC'+B'C)+ABC

= A'BC'+A'B‘C+AB‘C'+ABC

7

4-4 Design Procedure

The design procedure of combinational circuits

State the problem (system spec.)

determine the inputs and outputs

the input and output variables are assigned symbols

derive the truth table

ed b

x

derive the simplifi

erive the simplified Bool

oolean functions

xan functionx

draw the logic diagram and verify the correctness

9

Functional description

Boolean function

HDL (Hardware description language)

Verilog HDL

VHDL

Schematic entry

Logic minimization

number of gates

number of inputs to a gate

Propagation delay

number of interconnection

limitations of the driving capaeilities

10

Cdde conversion example

BCD to excess-3 code

The truth table

11

The simplified functions

z = D'

y = CD +C'D‘

x = B'C + B‘D+BC'D'

w = A+BC+BD

Another i

mplementation

z = D'

y = CD +C'D' = CD + (C+D)'

x = B'C + B'D+BC'D‘ = B'(C+D) +B(C+D)'

w = A+BC+BD

13

0 + 0 = 0 ; 0 + 1 = 1 ; 1 + 0 = 1 ; 1 + 1 = 10

two input variables: x, y

two output variables: C (carry), S (sum)

truth table

15

S = x'y+xy'

C = xy

the flexibility for implementation

S=xÅy

S = (x+y)(x'+y')

S‘= xy+x'y'

S = (C+x'y')'

C = xy = (x'+y')x

16

Z

0

0

0

0

X

0

0

1

1

+ Y

+ 0

+ 1

+ 0

+ 1

C S

0

0

0 1

0 1

1 0

Z

1

1

1

1

X

0

0

1

1

+ Y

+ 0

+ 1

+ 0

+ 1

C S

0 1

1 0

1 0

1

1

• A full adder is similar to a half adder, but includes a carry-in bit from lower stages. Like the half-adder, it computes a sum bit, S and a carry bit, C.
• For a carry-in (Z) of 0, it is the same as the half-adder:
• For a carry- in(Z) of 1:

CS 151

The arithmetic sum of three input bits

three input bits

x, y: two significant bits

z: the carry bit from the previous lower significant bit

Two output bits: C, S

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S = x'y'z+x'yz'+ xy'z'+xyz

C = xy + xz + yz

S = zÅ (xÅy)

= z'(xy'+x‘y)+z(xy'+x'y)'

= z‘xy'+z'x'y+z(xy+x‘y')

= xy'z'+x'yz'+xyz+x'y'z

C = z(xy'+x'y)+xy

= xy'z+x'yz+ xy

20

Carry propagation

when the correct outputs are available

the critical path counts (the worst case)

22

Reduce the carry propagation delay

employ faster gates

look-ahead carry (more complex mechanism, yet

faster)

ÅB

carry propagate: P

= A

i i i

carry g

carry generate: G

xnerate: G

= A

= A

B

B

i i i

ÅC

sum: S = P

i i i

carry: C

= G +P C

i+1 i i i

C

= G

+P

C

1 0 0 0

C

= G

+P

C

= G

+P

(G

+P

C

)

2 1 1 1 1 1 0 0 0

= G

+P

G

+P

P

C

1 1 0 1 0 0

C

= G

+P

C

= G

+P

G

+P

P

G

+ P

P

P

C

3 2 2 2 2 2 1 2 1 0 2 1 0 0

23

Logic diagram

2x

Digitxl Circuits

propagation delay

25

xigital Cixcuits

Binary subtractor

A-B = A+(2’s complement of B)

M=0, A+B; M=1, A+B’+1

26

Overflow

The storage is limited

Add two positive numbers and obtain a negative

number

Add two negative numbers and obtain a positive

number

V = 0, no overflow; V = 1, overflow

Example:

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