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REASON (IST-2000-30193) Third Annual Report Workpackage 3

REASON (IST-2000-30193) Third Annual Report Workpackage 3. Raimund Ubar Tallinn Technical University r aiub@pld . ttu.ee. Tasks and Goals. WP3 is devoted to training in design for testability of SoC , and develop ing research skills and creativity by development of

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REASON (IST-2000-30193) Third Annual Report Workpackage 3

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  1. REASON (IST-2000-30193)Third Annual ReportWorkpackage 3 Raimund Ubar Tallinn Technical University raiub@pld.ttu.ee 3rd Annual Review Meeting Sinaia, Romania, February 21-22, 2005

  2. Tasks and Goals WP3is devoted to • training in design for testability of SoC, and • developingresearch skills and creativity by • development of • courses(Task 3.1), • tools(Task 3,2), • research scenarios(Task 3.3), and • dissemination of new methods and tools in tutorials, seminars and workshops(Task 3.4) 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  3. WP3 Timeline AGBOT Environment The development activities in T3.1, T3.2, and T3.3 were mainly related to new initiatives and AGBOT 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  4. New Activities in T3.2 & T3.3 • Task 3.2.Teaching, training and researchenvironment • Task 3.3.Research scenarios • Internet based “living pictures” for training(WP8) • development of research scenarios • Tool development for SW based lab research (WP3) • interfaces for joint use of tools • Educhip for HW based lab research(WP9) • software development for EduChip • Research scenarios for EduChip 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  5. Contribution to WP3 in 2004 TULC, TTU, WUT Tools T3.2 Teaching Materials T3.1 TULC, VSTU, IISAS, FEISTU BSU,TTU,WUT Research Scenarios T3.3 Training Actions T3.4 TTU, IISAS, TULC, FEISTU TTU,TUI,TULC IISAS, FEISTU, VSTU, LPU, WUT,BSU,TUS 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  6. Cooperation in 2004 Tools & Research Scenarios AGBOT TULC IISAS TTU TUI FEISTU WUT Training Actions VSTU PUB TUS TUL KTU BSU 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  7. Cooperation between other WPs Development of the research environment in cooperation with WP8 and WP9 Task 3.2 Tools SW/HW Environment WP9 Educhip WP8 Applets Task 3.3. Research training scenarios 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  8. Cooperation between other WPs Joint tutorials: WP10 Conferences MIXDES DDECS EWDTW BEC WP7 Sinaia WP2 Smolenice WP3 Task 3.1. Course development 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  9. Task 3.2. Tool integration Cooperation: IISAS, KTU, TTU, WUT, TULC High-Level ATPG KTU Optimization of Scan-Based DfT TULC University Software VHDL/Verilog/System C ISCAS Benchmarks Logic synthesis Synopsys/Cadence VHDL-DD ISCAS Netlist EDIF-ISCAS Gate-Level EDIF Defect/Fault Analysis WUT DefGen/Delay IISAS DD Defect Library EDIF-SSBDD Turbo-Tester TTU Hierarchical ATPG Test Set SSBDD 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  10. Algorithms: Deterministic Random Genetic Levels: Gate Macro RTL Circuits: Combinational Sequential Formats: EDIF AGM Multivalued Simulation Faulty Area Defect Library Logic Simulation Test Generation Specifi- cation Test Set Design Fault Simulation BIST Emulation Methods: BILBO CSTP Hybrid Fault models: Stuck-at faults Physical defects Hazard Analysis Data Design Error Diagnosis Test Set Optimization Fault Table Lab Research Env. - 1 Task 3.2 Tools for test generation and fault simulation 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  11. Task 3.2 Lab Research Env. - 2 Educhip based Cooperation: IISAS, TTU, WUT DefGen, Turbo Tester, etc. Manual patterns Random patterns Deterministic SAF patterns Deterministic defect-patterns DefSim User Interface DefSim software (firmware, drivers) DefSim Chip 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  12. Combining on-line generated pseudo-random patterns with pre-generated and stored test patterns Problems : To find the best characteristics for test generator (PRPG) To find the best level of mixing pseudo-random test and stored test as the tradeoff between memory cost and testing time Task 3.3. Scenario: Hybrid BIST Hybrid BIST: SoC ROM . . . Core Test Generator . CORE UNDER TEST Controller Response Analyzer 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  13. Optimization of Hybrid BIST Cost curves for BIST: r (k) r (k) k FC(k) t(k) DET NOT 1 155 839 15.6% 104 2 76 763 23.2% 104 C Total Cost 3 65 698 29.8% 100 C Number of remaining TOTAL 4 90 608 38.8% 101 faults after applying k 5 44 564 43.3% 99 pseudorandom test 10 104 421 57.6% 95 patterns r (k) NOT 20 44 311 68.7% 87 Cost of 50 51 218 78.1% 74 pseudorandom test patterns C 100 16 145 85.4% 52 GEN 200 18 114 88.5% 41 411 31 70 93.0% 26 Cost of stored 954 18 28 97.2% 12 test C MEM 1560 8 16 98.4% 7 2153 11 5 99.5% 3 3449 2 3 99.7% 2 4519 2 1 99.9% 1 L 4520 1 0 100.0% 0 LOPT 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  14. Test patterns are stored Random resistant Deterministic in the memory faults test set T 3.3. Sc: Hybrid Functional BIST Deterministic test Functional test MUX MUX Automatic Automatic M M Test Pattern Test Pattern Generator Generator Register Register ALU ALU block block Signature Signature analyser analyser K K Data Publications:MIXDES’2004, ETS’2005 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  15. Genetic Optimizer Circuit Model LFSR Config. TTU WP8: BIST Applet BIST Emulator Synthesis Tools IISAS Estimated Growth of Complexity DfT Structure (VHDL) Circuit Model (VHDL) Other Fault Table Test Set Task 3.3. Scenario: BIST design Cooperation: IISAS, TTU Polynomial, Initial state • To be compared: • genetically optimized vs. manually obtained LFSR • original vs. “BISTed” device complexity 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  16. Events in 2004 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  17. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  18. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  19. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  20. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  21. Events in 2004 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  22. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  23. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  24. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  25. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  26. Events in 2004 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  27. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  28. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  29. Events in 2004 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  30. Events in 2004 In total: 18 international events out of 21 11 different countries 15 joint events 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  31. Geography of Events 4 1 4 1 1 1 2 1 2 1 3 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  32. Geography of Lecturers 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  33. Participants 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  34. Evaluation results 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  35. Other activities in 2004 • AGBOT – Handbook of Testing (397 pages) • 1.Introduction2.Defects, faults and fault models 3. Test generation techniques and algorithms 4.Design for testability5.Built-in self-test6.On-line testing7.IDDQ testing.8.Analog test and diagnostics9.Appendix 1: Tools, that can be used for practical exercises10.Appendix 2: Philosophy of Mentor test tools • The reviewing process is running and simultaneously the reviewed chapters are being formatted for printing. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  36. 3rd Annual Review Meeting Sinaia, Romania, February 21-22, 2005

  37. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  38. Other activities in 2004 • IEEE EWDTW - joint East-West event in D&T • Bringing expert skills from West to East • Y. Zorian (USA)Virage Logic and TTTC - Embedded Test for SoC • Ch. Landrault (France) LIRMM -Memory testing • B. Magnhagen (Sweden) DixiCAD- Optical testing • Knowledge transfer from East to West • Many experts from leading scientific centers of Russia, Ukraine, Byelorussia shared their knowledge with conference participants • Russian Test Tour • REASON: 7 lecturers from FEISTU, TTU, TUI, VSTU, WUT • RUSSIA: Vladimir, Tomsk, Irkutsk, Vladivostok (134 participants) • Meetings - Lviv, Liberec, Lodz, Prague, Bratislava, Sofia 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  39. Main achievements: Cooperation • To increase the synergy of the project, tight linkscreated to • WP8 (distance learning) and • WP9 (hardware based experimental research teaching) • WP10 (linking tutorials to conferences: MIXDES, BEC, DDECS, EWDTW • New links (in 2004): WP2, WP7 (joint tutorials) • Continuous extension of the Task 3.2 • 2003: from tool development to creation ofresearch training environment • 2004: web based access to the environment • AGBOT – a great book on testing • partners: FEISTU, IISAS, TTU, TULC, VSTU (14 authors) • a special AGBOT server set up by TULC in order to simplify collaboration New: • broader scope, compared to existing books • tools for laboratory research • theoretical support for Educhips, new lab conception • a book for teachers • 2-3 times cheaper than IEEE/Kluwer books • Intensive joint research - 12 joint publications(8 – 2002, 5 - 2003) 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  40. Main achievements: Training • 21 tutorials and training actions on Digital and Analog SoC Testing were organized in 11 countries • 15 joint tutorials, given by the partners from FEISTU, IISAS, TTU, TULC, VSTU, and WUT • 2 WP3 tutorials included into the TTTC TTEP database • Expert skills from IEEE and western industry were drawn (in 3 events): • the world leaders in test Y.Zorian (USA), Ch. Landrault (France) were invited to support REASON events at EWDTW in Ukraine • many other western VIPsoutside REASON(A.Jerraya, W.Hartenstein, T.Vierhaus, M.Renovell, B.Magnhagen, M.Glesner, H.Tenhunen, S.Kumar) consortium were invited to tutorials in Slovakia and Estonia • a Teaching Tour to Russia was organized in Sept with more than 15 lectures in 4 events all over Russia from Vladimir to Vladivostok • Knowledge transfer from East to West • Parts of the REASON WP3 tutorials were invited to be presented in Sweden and Germany (summer school) • MSc and PhD students from West to East 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  41. Responses to the 2nd review • While the development of 14 tools has been useful to the project, the long terms use will require long-term support. The developments w.r.t. intellectual property should be safeguarded. Commercial alternatives are more suitable for long-term use • The “home made” tools are the results of research which is ongoing, in this way the tool environment is kept alive and continuously updated • good possibility to involve students in research and in updating and improving the tools • because of the web based user access to tools, the support is easier • switching from “home made” to commercial can always be madeif possible 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  42. Responses to the 2nd review • Links and interfaces between the 14 software tools to be improved and clearly documented. Users must have a clear view of the global testing path • The interfaces between partner tools have now been created • also the interfaces and converters to commercial tools are available (EDIF, VHDL, Verilog, System C) • Benefits for industry to be clarified and/or improved • Competence Centre of MissionCritical Embedded Systems (ELIKO) has been created (with contracts between 7 private companies, 2 res. institutions under leadership of TTU) • in this centre currently 2 test oriented joint projects with industry covering REASON WP3 topics are running 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  43. Main goals for 2005 • AGBOT: Completing the Handbook on Testing • Completing the development ofresearch environment(incl. Educhip) • Development and update of a series of research scenarios • Special target:Hands-on lab courses for partners with partner tools • Testing the research scenarios • A series of tutorials and courses planned: • Lecture course in Sweden, Febr-March • Tutorial at DDECS, April 18, Sopron • 2 tutorials at European Test Symposion, May 21-25, Tallinn • 1-day tutorial on VHDL, June, Liberec • Special session on Educhips at MIXDES • Other hands-on training sessions • WP3 Workshop, May 20, Tallinn 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

  44. Conclusions • Intensive cooperation has been the target,local actions were less important • Joint courses, tutorials and tool environments • Joint research scenarios • Joint work on the textbook: AGBOT • Joint research – 12 joint publications (side effect) • Visibility of the WP3 team at the European level is increased 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

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