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ITRS Factory Integration (FI) Update

ITRS Factory Integration (FI) Update.

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ITRS Factory Integration (FI) Update

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  1. ITRS Factory Integration (FI) Update July 2007 Meeting Attendees: Daniel Babbs, Michio Honma, Melvin Jung, Al Chasey, Mani Janakiram, Tom Jefferson, Shige Kobayashi, Bill Miller, Mikio Otani, Mutaz Haddadin, Gopal Rao, Dave Eggleston, Kandi Collier, Makoto Yamamoto, Adrian Pike, Phil Naughton, Mahmoud Aghel, Takayuki Nishimura, Brad Van Eck, Eric Englhardt, Andreas Neuber, Rex Wright, Terry Francis, James Moyne, Bevan Wu Mani Janakiram July 2007 San Francisco, CA FI Global Co-Chairs: Europe: Arieh Greenberg Japan: Shige Kobayashi, Michio Honma Korea: C. S. Park, S. H. Park Taiwan: Thomas Chen US: Mani Janakiram

  2. Agenda • Scope and Difficult Challenges • Technology Requirements & Potential Solutions • 2007 Updates Summary • Top FI Focus Areas Summary • Factory Integration Cross-Cut Issues • Summary

  3. UI Factory Integration Scope and Drivers Factory Operations Production Equipment Factory Information & Control Systems AMHS Facilities Si Substrate Mfg Chip Mfg Wafer Mfg Product Mfg Distribution Reticle Mfg • FEOL • BEOL • Probe/Test • Singulation • Packaging • Test Increasing cost & Cycle time implications • Factory is driven by Cost, Quality, Productivity, and Speed • Reduce factory capital and operating costs per function • Faster delivery of new and volume products to the end customer • Efficient/Effective volume/mix production, high reliability, & high equipment reuse • Enable rapid process technology shrinks and wafer size changes

  4. Key Technologies that will Impact Factory Design • 2007 and future years were targeted to meet productivity and capture technology requirements • Key process & device technology intercepts that will impact the factory design are Extreme Ultraviolet Litho (EUVL), New Device Structures, new materials, wafer size conversion & huge productivity improvements • Economic and business challenges are equal to our manufacturing and process technology challenges in scope and breadth to attain efficiency and effectiveness Planning for 300’/450mm EUVL in Production? New Device Structures? Next Wafer Size in Production?

  5. FI Sub team –2007 Update

  6. 2007 FI Focus Area Summary

  7. Next Generation 300’/450mm Guidelines 2005 2006 2007 2008 2009 2010 2011 2012? Interoperability Testing & Reliability Verification 5 6 NG Factory Guidelines combined with ITRS TR & PS Factory Control System Standards 4 Direct Transport Standards STK STK 300mmプライム推進派 ISMI Guidelines JEITA Guidelines Wafer by wafer Process Start Speed etc Seasoning etc Production Equipment Standards 450mm wafer Standards Tool Tool Carrier & lot-size determination Wafer Point Of View 2005 2006 2007 2008 2009 2010 2011 2012 2 Source XTime Dest XTime Inter-Bay XTime Source Tool Wait Time Source STK Wait Time Dest STK Wait Time Dest Tool Wait Time Equipment maker Inputs 3 ITRS FI will work on combined 300’/450mm guidelines to address FI challenges, technology requirements and potential solutions Courtesy: JEITA/ISMI

  8. Processing Standby Standby/processing =100% Electric power (kW) 80 70 Standby/processing =75% 60 1:1 RATIO 50 Time Average effective electric power during standby (kW) 40 30 20 10 0 0 10 20 30 40 50 60 70 80 Average effective electric power during processing (kW) Energy conservation/ Equipment Sleep Mode Reduce facility operation cost by enabling facility demand based utilization model – including energy conservation • Align on Idle mode definition • Select tools for Sleep mode • Engage others to define solution Courtesy: Factory Facilities/Toshiba/SEAJ

  9. Factory Integration Roadmap Yield Enhancement Roadmap Fab environment Technology Requirements Wafer/Tool environment Wafer AMC Concepts and Requirements from FI perspective • AMC limits are addressed in the YE TWG, and the WECC sub TWG • Fab environment requirements are being defined in the FI TWG • Equipment, AMHS and FOUP • AMC monitoring & control Courtesy: YE / WECC

  10. Process View Tool View Product View Semiconductor Factory Step 1 Logical World Product Business Type Quality Tool 1 Area A Product Cost Common Process Group A Process Delivery Physical World How well is it realized? ESH Capacity Understanding Assumptions Understanding Results Products/Process Factory Operation Resources Understanding Activity In-Competitive Area Competitive Factory Visualization Metrics Key Indicators GOAL: Provide measurable/actionable metrics for managing factory at various levels easily Courtesy: STRJ

  11. <8> Abnormal • Detection • Wafer Restore • Trouble Restore • <4> Eqp Conditioning • Dummy Wafer Setting • Vacuuming • Heating • Seasoning 25 • <3> Set-ups • Reticle Settting • Ion Source Changing • <5> Quality Conditioning • Send-Ahead • Inspection Results Wait • Monitor Setting 20 15 • <2> Recipe Setting • Recipe Down Load • Variable parameter Setting • <6> Actual Process • Processing • Wafer Handling 10 Processing Time 5 • <1> Start • ID Read • Docking • Door Opening • Wafer Mapping • <7> End • Door Close • Undocking y = ax + b b 15 10 5 25 20 # of Wafers in a Carrier (lot?) Enhance Visibility of Equipment Activity • FI is working on putting the equip eng data contents in ITRS tables • Required for data contents meeting the equipment performance needs • Required for enhanced equipment quality management and assurance • Text on equip eng data contents included in 2007 FI text SECS data port exist – raw data Equip eng data content requested  model based data + activity/event data (energy, B/A, Setup time, etc.) setup time contributors Impact of equip intrinsic cycle time loss defined by a model Courtesy: STRJ

  12. FI Cross Cut Issues to be addressed

  13. Layout Test data Packaged IC Device models Circuit architecture Design rules Layout with critical paths Test data Packaged IC Organizational, corporate cultural and geographical barriers Circuit architecture Device models Designers Design rules Wafer fab Masks Masks optimized based on design intent Role of PCS/APC? Statistical timing optimization Process variation distributions Designers Known contours of CD, topography or overlay error with mfg. process Wafer fab LWR = Line Width Roughness; LER = Line Edge Roughness ITRS Litho Challenges/Needs New mode of operation with design for manufacturing (DFM) practices • Design for Mfg (DFM) needed for: • Immersion litho challenges • Double Patterning needs • EUVL challenges • Controlling LWR and LER increasingly important • Stringent overlay tolerances needed Present mode of operation for circuit design and fabrication DFM Integration of design, modeling, lithographic resolution enhancement techniques and extensive metrology needed to maintain expected circuit performance Source: Based on ITRS Litho TWG

  14. Factory Integration Summary • All FI technology requirements tables and potential solutions tables updated • Operations, Equipment, AMHS, FICS and Facilities • Identified key focus areas for FI • Technology requirement and potential solutions for 300’/450mm • Equipment sleep mode • Intrinsic equipment losses and better visibility of data • AMC solutions for equipment and FOUP • Working with other TWG on cross-cut issues • With FEP, Litho, Metrology, Yield Enhancement and ESH • EUVL, single wafer processing, IM, energy conservation, etc. • Business strategies, market demands, and process technology changes continue to make factories difficult to integrate • Work with other forums/WG to ensure synergy • ISMI 450mm WG, STRJ, IMA, JEITA, SEMI, etc. • Improve sub-team participation to obtain cross-synergy Thanks!

  15. Backup

  16. Solution exists Solution being developed Solution required Factory Operations Technology Requirements Key Objectives: Speed & Flexibility 1) Reduce mfg cycle times, 2) Improve Equipment Utilization, 3) Reduce Losses from High Mix

  17. Production Equipment Technology Requirements Key Objectives: 1) NPW reduction, 2) Reliability Improvement, 3) Run rate (throughput) improvement  Productivity & Cost Solution exists Solution being developed Solution required

  18. Material Handling Technology Requirements Key Objectives: 1) Increase throughput for Traditional and Unified Transport, 2) Reduce Average Delivery times, 3) Improve Reliability Solution exists Solution being developed Solution required

  19. FICS Technology Requirements Key Objectives: 1) Increase Reliability, 2) Increase Factory Throughput, 3) Reduce or Maintain Mask Shop Cycle Time, 4) Reduce Costs Solution exists Solution being developed Solution required

  20. Facilities Technology Requirements Key Objectives: 1) Factory Extendibility, 2) AMC, 3) Rapid Install/Qualification, 4) Reduce Costs Solution exists Solution being developed Solution required

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