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設計驗證工作室 Design Verification Team

設計驗證工作室 Design Verification Team. 黃鐘揚 教授 Prof. Chung-Yang (Ric) Huang Department of Electrical Engineering National Taiwan University 2008/02/14. Lab Profile. Founded in 2004.02 Lab info Office: EE-II 444 Lab: EE-II 353 PTT: NTUGIEE_ric Website: http://dvlab.ee.ntu.edu.tw/

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設計驗證工作室 Design Verification Team

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  1. 設計驗證工作室Design Verification Team 黃鐘揚 教授 Prof. Chung-Yang (Ric) Huang Department of Electrical Engineering National Taiwan University 2008/02/14

  2. Lab Profile • Founded in 2004.02 • Lab info • Office: EE-II 444 • Lab: EE-II 353 • PTT: NTUGIEE_ric • Website: http://dvlab.ee.ntu.edu.tw/ • To find me… • ric@cc.ee.ntu.edu.tw • ric2k1 @ ptt, ptt2, msn, skype, ... • 02-3366-3644 Chung-Yang (Ric) Huang http://dvlab.ee.ntu.edu.tw +886-2-3366-3644

  3. Research Focus • EDA: Electronic Design Automation • Develop algorithms and tools for circuit design automation and optimization • Design implementation: logic and physical synthesis and optimization • Design verification: assuring the correctness of the implementation • Design analysis: evaluating the performance and robustness of the design Chung-Yang (Ric) Huang http://dvlab.ee.ntu.edu.tw +886-2-3366-3644

  4. What is Design Verification? always @(posedge clk) begin if (rst==1'b1) cnt <= sv; else if (cnt==2'b00) cnt <= 2'b01; else if (cnt==2'b01) cnt <= 2'b10; else if (cnt==2'b10) cnt <= 2'b11; else cnt <= sv; end for (i = 0; i < d; i= i+2) { if (y > 3) p = p * 3; else q = q + r; } Bottom line: to fix as many bugs in your design as possible Verification takes ~ 70% of resources in today’s IC design Chung-Yang (Ric) Huang http://dvlab.ee.ntu.edu.tw +886-2-3366-3644

  5. Design verification can be... • Very engineering! • Simulation-based approach • Apply input patterns and verify if outputs are correct  But how many patterns can you try? What’s the %? • If a bug is found... • Study the waveform  Exam the signal values  Trace the code  Fix the potential causes  Try again...  Do you fix the bug? Any side effect? bugs found ??? time Chung-Yang (Ric) Huang http://dvlab.ee.ntu.edu.tw +886-2-3366-3644

  6. Expected Behavior e.g. Always (req  ack) Design verification can be... A mathematical / logic reasoning engine is required!! • Very theoretical... • Formal verification Design Under Verification (DUV) Check consistency Arithmetic / Logic Model (Constraints) Properties Chung-Yang (Ric) Huang http://dvlab.ee.ntu.edu.tw +886-2-3366-3644

  7. AP1 AP1 AP1 AP1 Firmware Driver JPEG-Encode RGE-YCrCb JPEG-Encode RGE-YCrCb HW/SW Co-design Co-Verification RTOS HW Virtual Platform cache Processor DSP DMA ROM RAM Design verification can be... • Defining the design methodology!! • What is “System-on-Chip” (SoC)? • What is system-level design methodology?  No good / established EDA tool flow yet... (How can design verification play a deciding role?) Chung-Yang (Ric) Huang http://dvlab.ee.ntu.edu.tw +886-2-3366-3644

  8. 3 Research Teams • Front-end Team • Intelligent design debugging • Formal-based design optimization • Formal Engine Team • Circuit-based Boolean Satisfiability (SAT) solver • High-level (arithmetic) solver • Electronics System Level (ESL) Design Team • SoC virtual platform • System-level EDA tools Chung-Yang (Ric) Huang http://dvlab.ee.ntu.edu.tw +886-2-3366-3644

  9. 5 On-going Projects • 電子系統階層之正規模型與最佳化研究 • Formal Modeling and Verification of Electronics System Level Designs, 思源科技 • 正規驗證輔助電路最佳化 • Formal-Assisted Technology Dependent Logic Optimization, 思源科技 • 低溫多晶矽數位電路元件資料庫之建立與驗證 • Cell Library Construction and Verification for LTPS-TFT Digital Circuits, 友達光電公司 • N-MoIP: 適用於異質無線網路環境之前瞻 MoIP 手持裝置 SoC 設計 • N-MoIP: SoC Design of Advanced Multimedia-over-IP Handheld Device for Heterogeneous Wireless Network Environments, 國科會國家型SoC計畫 • 兆級晶片系統前瞻技術研究-子計畫七：兆級晶片系統模擬與正規驗證之整合技術 • Combining Simulation and Formal Verification Techniques for Trillion-transistor-Scale System-on-Chip (TS-SoC), 國科會整合型計劃 More are coming soon!! Chung-Yang (Ric) Huang http://dvlab.ee.ntu.edu.tw +886-2-3366-3644

  10. 工號 姓名 加入年月 Title ---------------------------- 0 黃鐘揚 2004.02 老闆 1 林庭豪 2004.02 博 3 2 葉護熹 2004.05 博 3 9 李智群 2004.12 RA 11 蔡詩蘅 2004.12 博 2 13 劉惠芳 2005.04 碩 2 14 葉昱甫 2005.06 博 3 15 湯凱富 2005.06 博 3 16 吳濟安 2005.11 碩 2 17 粘敬佳 2005.11 碩 1 18 黃紹倫 2005.12 博 2 19 周俊男 2005.12 博 2 20 吳鎧竹 2005.12 碩 2 21 李沅龍 2006.04 碩 2 22 胡啟政 2006.04 碩 2 23 饒瑞晞 2006.11 碩 1 24 葉鎮丞 2006.11 碩 1 25 許智仁 2006.11 碩 1 26 林坤輝 2006.11 碩 1 27 蔡曉傑 2006.11 碩 1 28 賴昭宇 2007.09 RA 29 吳政穎 2007.11 碩 0 30 左佳正 2007.11 碩 0 31 徐常紘 2007.11 碩 0 32 林恩祥 2007.12 碩 0 ---------------------------- 藍字: NTUEE 綠字: NTUCS 實驗室成員 博班: 7, 碩班: 11, 研究助理: 2, 專題生: 4 Chung-Yang (Ric) Huang http://dvlab.ee.ntu.edu.tw +886-2-3366-3644

  11. 給專題生的建議 • 如果是想出國念 EDA, 希望我寫推薦信的... • 歡迎!! 但是請投注足夠的心力在我的專題上. • Best recommendation letters are for best students. • 如果想出 paper 的要明講, 並且態度要夠積極! • 原則: 以 first author 的 paper 優先考慮 Chung-Yang (Ric) Huang http://dvlab.ee.ntu.edu.tw +886-2-3366-3644

  12. 給專題生的建議 • 如果是想多了解 EDA 這個領域的... • 歡迎!! 但是請去修 “EDA 概論”, 並且建議修我的 “資結與程設” • Formal verification 的 research 是有一定門檻的 • 並且建議參加 CAD 競賽 • http://lads.ee.ntu.edu.tw/cad08/index.htm • 如果是有興趣加入我們實驗室的... • 歡迎!! 早點修我的專題會被優先考慮喔!! • 當然, 請不要用混的~~~ Chung-Yang (Ric) Huang http://dvlab.ee.ntu.edu.tw +886-2-3366-3644

  13. AP1 AP1 AP1 AP1 RTOS HW cache Processor DSP DMA ROM RAM Firmware Driver Potential Topics for 專題生 • ESL Design Methodology • 適合對象: • 想了解 EDA,或是 想加入我們實驗室 的人 • 條件: • 對基本的 IC design flow 有點概念, 或學過 Verilog 的人為佳 • 內容: • 了解 SoC design methodology • 學習 SystemC (以 C++ 為主的 ESL language) • 參與 QuteVP virtual platform 的實作 • 參加 weekly ESL study group Chung-Yang (Ric) Huang http://dvlab.ee.ntu.edu.tw +886-2-3366-3644

  14. Potential Topics for 專題生 • Formal engine (theorems and algorithms) • 適合對象: • 想出國唸書, 或是 想加入我們實驗室 的人 • 條件: • 能作數理的抽象思考, 有創意者為佳. • 內容: • 了解 formal verification 的原理 • 建議修: SoC Verification • 參與 QuteSAT or CNF SAT engine 的改進計畫 • 參加 weekly engine study group • 獨立完成一個題目而且能寫 paper Chung-Yang (Ric) Huang http://dvlab.ee.ntu.edu.tw +886-2-3366-3644

  15. Potential Topics for 專題生 • Open Verilog front-end release • 適合對象: • 想了解 EDA, 或是 想出國唸書 的人 • 條件: • 有產品行銷的 sense, 能執行 product release 者為佳 • 了解 Verilog 語法者為佳 • 內容: • QuteRTL framework 之實作 • 參與 QuteRTL open Verilog research framework 之 release • Target: DAC 2008 University Booth (June, San Diego) • EDA product software engineering + marketing 之訓練 • We are serious about the framework release !! • 支援其他實驗室對此 framework 之要求 Chung-Yang (Ric) Huang http://dvlab.ee.ntu.edu.tw +886-2-3366-3644

  16. Potential Topics for 專題生 • Intelligent Chip (iChip) 之 Automatic Learning Pattern Generation • 適合對象: • 有勇氣挑戰未知領域的熱血青年 !! • 條件: • 習慣天馬行空卻又有真正執行力者為佳 • 內容: • 參與陳良基教授主持之 “iChip”國科會三年期整合計畫 • What’s the HW architecture for the intelligent chip? • 熟悉 formal verification engine 的原理 • 參考 “人工智慧”之文獻 • 涉獵 教育, 心理, 生理 等科學 • Ideas 之討論與實驗 Chung-Yang (Ric) Huang http://dvlab.ee.ntu.edu.tw +886-2-3366-3644

  17. Potential Topics for 專題生 • 其他  就是以上沒有你真正想做的, 但是又很想跟我做專題 (有這種人嗎?) • 可以多了解我們實驗室目前在做的計畫 • 或是你有自己的 idea • 領域不限, 歡迎切磋 • 或是你想參加 CAD 競賽卻沒有指導教授... Chung-Yang (Ric) Huang http://dvlab.ee.ntu.edu.tw +886-2-3366-3644

  18. 專題生的福利 • 原則上專題生沒有薪水, 除非你自己有提國科會計畫 • 也有例外: Full-time RA; or special mission • 實驗室的資源歡迎利用 • 工作站, notebook, printers, paper DB, EDA tools, etc. • 不過沒有專屬的位子, 有空位就坐. • 實驗室的 “吃喝玩樂”歡迎參加 • 聚餐, team building events, 出遊, etc. • 用 Google Calendar 預約 meeting 時間 Chung-Yang (Ric) Huang http://dvlab.ee.ntu.edu.tw +886-2-3366-3644

  19. For more information...http://dvlab.ee.ntu.edu.tw Chung-Yang (Ric) Huang http://dvlab.ee.ntu.edu.tw +886-2-3366-3644

  20. For more information...PTT  NTUGIEE_ric Chung-Yang (Ric) Huang http://dvlab.ee.ntu.edu.tw +886-2-3366-3644

  21. For more information...Lab DB (password required) Chung-Yang (Ric) Huang http://dvlab.ee.ntu.edu.tw +886-2-3366-3644

  22. For more information... • To find me • Office: EE-II 444 • ric@cc.ee.ntu.edu.tw • ric2k1 @ ptt, ptt2, msn, skype, ... • 02-3366-3644 • Lab: • EE-II 353 • PTT: NTUGIEE_ric • Website: http://dvlab.ee.ntu.edu.tw/ Chung-Yang (Ric) Huang http://dvlab.ee.ntu.edu.tw +886-2-3366-3644

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