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The Technology Leader in Front-End Physical Design. Yesterday’s Chip is Today’s Partition. Hierarchical Implementation is Imperative!. Full Chip SoC. Partition (Yesterday’s Chip). Block. New “Direct Approach” Hierarchical Partition. New Solution (Direct Approach). 10MgDesign Data.

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yesterday s chip is today s partition
Yesterday’s Chip is Today’s Partition

Hierarchical Implementation

is Imperative!

Full Chip SoC

Partition

(Yesterday’s Chip)

Block

new direct approach hierarchical partition
New “Direct Approach” Hierarchical Partition

New Solution

(Direct Approach)

10MgDesign

Data

Conventional Solution

(Trial-and-Error Approach)

Hier. Locality Placement

Ultra fast detail route

Chip-Level timing analysis Optimize floorplan

Guesstimate

Floor Plan

Manual:

Pin Assign

Partition Area

Risk :

Non-Convergence

Extract:

Partition Area

Aspect Ratio

Pin Assign.

Indep. Partition’s

P&R, Timing Opt

Indep. Partition’s

P&R, Timing Opt

Risk : Die size Penalty

Optimal Die size

Optimal Timing

Guarantee Easy Convergence

logical and physical interaction for fast design closure
Logical and Physical Interaction for Fast Design Closure

P&R and Timing Engine

  • Unified Placement and Floor Plan (Guide)
  • Logic hierarchy maintained in physical domain
  • Controllable/Predictable
  • Superfast detail trial route

Front-End Design

Physical Design

  • Create Physically Realizable RTL
  • Synthesize Physically Feasible Netlist
  • Create Physically Implementable Floor Plan “Guide”
  • Final Timing
  • Die Size
  • Power
  • CTS
  • Signal Integrity
slide5

Progressive Convergence

“Shifting Gears” With One Integrated, Full-Featured Physical Design Engine

Same Familiar Design Flow

Partition

+

FP

Place

+

Opt

Detail

Router

SYN

GDSII

Physical

Reality

Physical

Feasibility

Physical

Controllability

Requirements:

Speed

Accuracy

Ease-of-Use

Capacity

Hierarchical

Gear Box

Hierarchical Physical Design

Timing

Optimization

Analysis

One Integrated Engine

slide6

Competing Strategies for DSM Design Closure

SYN

+

Place

Route

FP

Place

(A)

Top Down Approach : Front-end Heavy

TraditionalFlow

SYN

+

Place

FP

SYN

Route

FP

SYN

P&R

(B)

Bottom-up Approach : Back-end Heavy

Partition

+

FP

+

Phys

Reality

Place

+

OPT

+

CTL

SYN

+

Phys

Feasibility

Route

(C)

Progressive Convergence Approach :

Front-end & Back-end in Tandem

golden metrics for emerging eda tools
“Golden Metrics” for Emerging EDA Tools
  • Long Term Survival Tests:
    • Ease-of-Use/Intuitive
    • Minimum Set-Up Time
    • Fast Turn-Around Time
    • Multi-Million Cell Capacity
    • Hierarchical Solution
  • Minimum Change to Existing Design Methodology
    • Utilize Existing Tool Investment ($, training, etc.)
    • Min. Realignment of Logic/Physical Designer Duties
    • Quick Implementation into Design Flow
  • Production Proven on Many Critical and Large Projects
slide8

First EncounterTM

Super-Light Weight Front-End

Physical Design EnvironmentTM

  • New class of fully integrated tools
  • Built around Fast-Track DatabaseTM
  • So fast, “iterations” become
  • “interactions”
  • Co-Optimize timing, power, area,
  • route-ability, and partition
slide9

First EncounterTMDesign Flow

Partition

+

FP

Place

+

Opt

Detail

Router

SYN

GDSII

Physical

Reality

Physical

Controllability

Physical

Feasibility

Gear Box

Analysis (RC, DC, TA, Power, EM, SI)

Analysis (RC, DC, TA, Power, EM, SI)

Hier

Partition

Global

Timing

Mgmt

Unified

FP/Place

Timing

Control

T.D.

Place

Timing

Refine

Hier

Partition

Global

Timing

Mgmt

Unified

FP/Place

Timing

Control

T.D.

Place

Timing

Refine

IPO

Timing

Closure

IPO

Timing

Closure

CTS

CTS

Detail Trial Router

Detail Trial Router

slide10

What do we mean by

“Super-Light Weight”?

another example of super light weight
Another Example of “Super-Light Weight”

900K cells (approx. 3.5Mg) + 31 blocks

  • Design Import and Flatten 10 Min.
  • Placement (fast-mode) 4 Hrs.
  • Trial Route 40 Min.
  • Full-chip RC Extraction + SDF 35 Min.
  • Max. Memory Requirement 1.37 GB.
key enabling technology amoeba tm
Key Enabling Technology - AmoebaTM

Intelligent Hierarchical Locality-Based Placement Engine

  • Maintains Locality at Every Level of Hierarchyw/o Fencing
    • Good initial timing solution
  • Makes Physical Layout Intuitive for Logic Designers
    • Effective communication medium between logic/physical teams
  • Predictable and Controllable Results
    • Coupled with floorplan “guidance” for predictability
    • Timing integrity maintained each iteration

Traditional Placement

Amoeba Placement

slide15

Floor Plan View Generated From Amoeba

Placement and Floor Planning Become ONE!

slide18

3.6M Gate Design - 8 Logical Partitions

  • Fully integrated with First Encounter Environment
  • Starts with known placeable/routable solution
  • Optimum partition aspect ratios and sizes
  • Easily accommodates modules growing /shrinking
  • Seamless chip and block level design convergence
slide19

Partition Optimizer Intelligent Pin Assignment

  • Intelligent automatic pin assignment
    • Aligned pins minimize channels
  • Automatic block feed-thru assignment
  • Top-level intelligent buffer insertion
slide20

...Partition Optimizer automatically generated optimal hierarchical partitions and assigned the pins based upon (the) initial physical route. The resulting die size savings of 10-15% is of major importance in a high-volume set-top box application.”Ram GollapudiDesign Center Manager, SJ Tech CenterVLSI Technology, Inc.

direct link to ultima dc tba
Direct Link To Ultima DC(TBA)

Driven by customers

Two parts joint effort :

- Calibrate First Encounter DC with Ultima DC

- Provide direct link from First Encounter to Ultima DC

Usage model :

- Fast mode using First Encounter DC / Calibrated

- High accuracy mode using Ultima DC

Benefits :

- Increased DC accuracy in First Encounter physical design system

- Consistent DC accuracy from physical design to final sign off

partial spc customer list
Partial SPC Customer List

Multimedia/Chipsets:

Networking:

  • AMD - MPD
  • S3
  • TeraLogic
  • Trident
  • VLSI Technology
  • SiS
  • AMD - NPD
  • Ardent Technologies
  • Broadcom (Maverick)
  • Marvell Semi.
  • Acute
sales and support offices
Sales and Support Offices
  • Silicon Valley
  • Taiwan (Eteam)
  • Austin/Texas (Feb. 2000)
  • Japan (Feb. 2000)
  • East Coast U.S. (Q1 2000)
  • Europe (Q2 2000 )
summary
Summary
  • SPC delivers First Encounter - TODAY
    • SoC “smart” hierarchical design/optimization solution
    • DSM physical design/optimization engine

with “quantum leap” in

Speed, Ease of Use, Accuracy, Capacity and Predictability/Controllability

    • Production quality software - silicon proven by many customers
  • SPC will continue to deliver the most advanced technology - TOMORROW
    • First Encounter lays a solid foundation for rapid development of future DSM design/optimization solutions