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ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems. Day 19: October 22, 2010 Pass Transistor Logic. Today. Pass Transistor Logic Muxes Performance Composition Logic Tristates. Behavior. O=S*A + S*/B. S. A. B. Delay. Assume R 0 /2 drive 10C 0 load

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ese370 circuit level modeling design and optimization for digital systems

ESE370:Circuit-Level Modeling, Design, and Optimization for Digital Systems

Day 19: October 22, 2010

Pass Transistor Logic

today
Today
  • Pass Transistor Logic
    • Muxes
    • Performance
    • Composition
    • Logic
    • Tristates
behavior
Behavior
  • O=S*A + S*/B

S

A

B

delay
Delay
  • Assume R0/2 drive
  • 10C0 load
  • What else need to know?
    • Cdiff=CSB or CDB
    • Assume Cdiff≈Cgate

5

2

5

capacitances
Day 10Capacitances
  • GS, GB, GD, SB, DB, SD
contact capacitance
Day 10Contact Capacitance
  • n+ contacts are formed by doping = diffusion
  • Depletion under contact
    • Contact-Body capacitance
  • Depletion around perimeter of contact
    • Also contact-Body capacitance
contact diffusion capacitance
Day 10Contact/Diffusion Capacitance
  • Cj – diffusion depletion
  • Cjsw – sidewall capacitance
  • LS – length of diffusion

LS

cmos delay
CMOS Delay
  • O=S*A + S*/B
what s different
What’s different?
  • What’s different about the output?
output ok
Output ok?
  • Is the output usable?
voltage drop
Voltage Drop
  • Voltage drop across any number of series transistors is one Vth
  • Think about two series transistors as one transistor of twice the length
pinch off
Day 9Pinch Off
  • When voltage drops below VT, drops out of inversion
    • Occurs when: VGS-VDS< VT
  • Conclusion:
    • current cannot increase with VDS once VDS> VGS-VT
    • current must adjust so that VDS= VGS-VT
    • If current dropped to zero, then would invert and conduct again…
performance
Performance?
  • Assume R0/2 drive
  • 10C0 load
  • Cdiff=Cgate

5

2

5

performance1
Performance
  • R0/2 drive
  • 10C0 load

5

2

5

performance2
Performance
  • R0/2 drive
  • 10C0 load
not isolating
Not Isolating
  • Does not isolate downstream capacitive load
  • Stage delay now dependent on downstream stages
power implications
Power Implications
  • What’s the power impact of partial swing?
back to rail
Back to Rail
  • How make it go to rail?
level restore
Level Restore
  • What issue arises here?
level restore1
Level Restore
  • What issue arises here?
tristate
Tristate
  • Sometimes want to be able to not drive a line
    • Bus driven from different places
    • I/O port – sometimes read, sometime write
next week
Next week
  • No new assignment now
    • (will get new one after midterm)
  • Class Monday
  • Midterm Wednesday
    • No lecture
    • Midterm 7-9pm in this room
  • Class Friday
midterm everything through today
Midterm(Everything through today)
  • Restoration
  • Implement or identify gate / logic function
  • Estimate performance for circuit
  • Estimate/reduce energy for circuit
  • Size transistors in gate/netlist
  • Variation impact
  • Scaling
  • Ratio and pass tr circuits fair game
  • Synchronous/clocking not on midterm
ideas
Ideas
  • There are other logic disciplines
  • We have the tools to analyze
  • Pass Transistor Logic
    • Possibly smaller, faster
    • Not rail-to-rail
      • Techniques to restore
    • Cascading without buffering  slow
    • Tristate Drivers
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