1 / 18

Interfacing Devices to the 68000

Interfacing Devices to the 68000. Interfacing devices. Read cycle timing parameters. Write cycle timing parameters Memory Device parameters Other device issues. Read cycle timing. For interfacing the arrows matter Indicate the precedence of signals for interfacing. Timing continued.

duscha
Download Presentation

Interfacing Devices to the 68000

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Interfacing Devices to the 68000 Lecture 12 - Interfacing Devices

  2. Interfacing devices • Read cycle timing parameters. • Write cycle timing parameters • Memory Device parameters • Other device issues Lecture 12 - Interfacing Devices

  3. Read cycle timing • For interfacing the arrows matter • Indicate the precedence of signals for interfacing Lecture 12 - Interfacing Devices

  4. Timing continued • For a slower device • How fast/slow a device can be interfaced? • tDALDI is 0 to 90ns • But this is FROM memory Lecture 12 - Interfacing Devices

  5. Parameters • Read cycle parameters Lecture 12 - Interfacing Devices

  6. Memory timing • Must consider timing of memory device Lecture 12 - Interfacing Devices

  7. Memory Pinout of the 6116 static RAM Lecture 12 - Interfacing Devices

  8. Items of note • Chip is 2K x 8-bit • Data word is a byte • Must use LDS* and UDS* when configuring memory with the device • In general memory chips are 1-bit, 1-byte, or 1-word in width of the data interface. Lecture 12 - Interfacing Devices

  9. Connecting up the 6116 Lecture 12 - Interfacing Devices

  10. Ended here on Monday 11/15 Lecture 12 - Interfacing Devices

  11. Combined 68000, 6116 timing Lecture 12 - Interfacing Devices

  12. The write cycle • Timing of processor and memory device must work for both reading device and writing device • It is possible that timing will work for read but not for write for a given device • I/O devices may be such that they are only written to or read from • Example: On modern motherboards you may need matched DIMMs in pairs for the faster memory access speeds. (4GB Dual Channel DDR3 RAM – PC12800, 1600MHz (2x2048MB) Lecture 12 - Interfacing Devices

  13. Write cycle timing Lecture 12 - Interfacing Devices

  14. Write cycle parameters Lecture 12 - Interfacing Devices

  15. Write cycle timing of 6116 Lecture 12 - Interfacing Devices

  16. 68000-6116 combination for write Lecture 12 - Interfacing Devices

  17. General notes • Can use memory or I/O devices that are designed for the processor family • Easy generation and use of interface pins such as CS*, AS*, DTACK*, etc. • Little glue logic (sometimes almost none) • Use of generic memory and I/O devices • May need a fair amount of glue logic and have to generate some signals • May be slower than family devices Lecture 12 - Interfacing Devices

  18. General methodology • Read cycle timing parameters and specifically those that matter in device interfacing • Then the same for write • Memory chip timing parameters and how they matches (or don’t) with what we havd Lecture 12 - Interfacing Devices

More Related