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ammar:. Branch & Pipelines. Branch & Pipelines. write. ifetch. read. compute. Bnch. write. ifetch. read. compute. Delay Slot. write. ifetch. read. compute. Branch Target. By the end of the read stage of the Branch instruction, the CPU knows
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ammar: Branch & Pipelines
Branch & Pipelines write ifetch read compute Bnch write ifetch read compute Delay Slot write ifetch read compute Branch Target By the end of the read stage of the Branch instruction, the CPU knows whether or not the branch will take place. However, it will have fetched the next instruction by then, regardless of whether or not a branch will be taken.
Delayed Branches: Redefine behavior Branch: Inst Fetch Dcd & Op Fetch Execute execute successor even if branch taken! Inst Fetch Dcd & Op Fetch Execute Inst Fetch Then branch target or continue Single delay slot impacts the critical path • add r3, r1, r2 • sub r4, r4, 1 • bz r4, LL • ... • LL: add rd, ... • Compiler can fill a single delay slot with a • useful instruction 50% of the time. • try to move down from above jump • move up from target, if safe
Delayed Branches (cont.) Execution History instr0 BCND X instr1 instr2 . . . X: PC nPC PC nPC PC nPC PC nPC Branch Not Taken Branch Taken t2' t1 t0 t2 Branches are the bane of pipelined machines Delayed branches complicate the compiler slightly, but make pipelining easier to implement and more effective Good strategy to move some complexity to compile time
