A Semi-Canonical Form for Sequential Circuits

1. A Semi-Canonical Form for Sequential Circuits Alan Mishchenko Niklas Een Robert BraytonUC Berkeley Michael Case Pankaj Chauhan Nikhil Sharma Calypto Design Systems

2. MOTIVATION • Logic circuits often contain duplicate sub-circuits expressed in terms of different primary inputs • This leads to redundant work • Synthesis tools repeatedly analyze the same sub-circuits • Verification tools repeatedly solve the same instances

3. MOTIVATION • Key idea: identify duplicate sub-circuits • Ideal solution: exact graph isomorphism • May be expensive and hard to implement • Our solution is heuristic • Find a semi-canonical circuit structure • Computation is similar to simulation • Efficient and straight-forward to implement • Uses only structural information • No need for signal names and user hints

4. EXAMPLE • Consider unique attributes of each node • Fanout count  {b}, {m} are unique • Complemented outputs  {c} is unique • Fanin level  {F}, {G} are unique

5. EXAMPLE • Nodes that cannot be uniquely identified belong to the same equivalence class • The above circuit has two equivalence classes of primary outputs: {F, F’}, {G, G’} G’ F’

6. AIG In this work, sequential circuits are represented as And-Inverter Graphs (AIGs) AIG is a Boolean network whose logic nodes are two-input AND-nodes and inverters Inverters are represented as complemented attributes AIG is a uniform and low-memory data-structure It allows for an efficient implementation of a variety of algorithms working on sequential circuits

7. ALGORITHM OVERVIEW • Structural signature of a node is an integer number computed for the node using its location in the circuit • Initially, signatures of all nodes are set to 0 • Circuit is repeatedly traversed and signatures are updated • Goal: assign unique signatures for as many nodes as possible • Motivation for computing unique signatures • If a node has a unique signature, it has been uniquely identified using its position in the circuit structure • A one-to-one mapping between the nodes of two circuits can be found using unique signatures of their nodes • If such mapping exists, the circuits are structurally isomorphic

8. ALGORITHM OVERVIEW • Signature propagation is similar to circuit simulation • During circuit simulation, values of the nodes are computed in a direct topological order • During signature propagation, signatures of the nodes are computed in a direct (or reverse) topological order • Edge value reflects the structure around an edge • Depends on the position (logic level) of the driving node • Depends on whether the edge is complemented or not • Each time a node is traversed, edge values of its fanins (or fanouts) are added to the signature of the node 8

9. ALGORITHM OVERVIEW 0 0 2 3 1 15 0 8 19 0 5 7 6 4 0 0 0 0 42 71 12 12 12 12

10. ALGORITHM OVERVIEW • When nodes cannot be uniquely identified using their structural signatures, tie breaking is used • Choose the equiv class with the largest level • Assign unique signatures to the class nodes • Propagate signatures to other nodes until convergence • If some equiv classes are left, repeat 71 42 15 15

11. IMPLEMENTATION • Computation of unique signatures is implementation in ABC • The unique signatures (which are integer numbers) are used to put nodes of a circuit in a semi-canonical order • When nodes are written into a file in this order, the resulting file is a semi-canonical form of the circuit • If files for two circuits are identical, the circuits are isomorphic • Application 1: ABC command “write_aiger –u” • Writes the netlist in a semi-canonical form • Application 2: ABC command “&iso” • Discards isomorphic POs

12. IMPLEMENTATION • Application 1: ABC command “write_aiger –u” • Writes the netlist in semi-canonical form • Useful for quickly comparing AIGER netlists Netlist N1 write_aiger -u N1.aig diff Netlist N2 write_aiger -u N2.aig

13. IMPLEMENTATION • Application 2: ABC command “&iso” • Derive a semi-canonical form for each PO • Discard POs that have duplicate semi-canonical forms • i.e. “drop isomorphic proof obligations” G’ F’ a' b’ c’ d’ • Counterexamples/invariants on F/G can be re-mapped to F’/G’

14. EXPERIMENTAL RESULTS • Use industrial verification benchmarks • Remove isomorphic POs • Apply synthesis, remove proved POs • Remove isomorphic POs (again) Initial AIG Statistics

15. CONCLUSION • Previous work focused on • computing functional symmetries and automorphisms • simplifying reachability and SAT using symmetries • To our knowledge, this is the first work on computing a structural semi-canonical form for sequential circuits • Allows for caching intermediate circuits in EDA tools • Future work may include: • Speeding up propagation of node signatures • Generalizing the algorithm to work for logic networks other than the traditional sequential AIGs

16. THANK YOU Public implementation is available in ABC https://bitbucket.org/alanmi/abc