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Combinational Circuit. Inputs. Outputs. Memory Elements. Combinational Circuit. Inputs. Outputs. Flip-flops. Clock. Sequential Circuits. Asynchronous Synchronous. Latches. SR Latch. Q = Q 0. 0. 0. 1. 0. Initial Value. Latches. SR Latch. Q = Q 0. Q = Q 0. 0. 1. 0.

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sequential circuits

Combinational

Circuit

Inputs

Outputs

MemoryElements

Combinational

Circuit

Inputs

Outputs

Flip-flops

Clock

Sequential Circuits
  • Asynchronous
  • Synchronous
latches
Latches
  • SR Latch

Q = Q0

0

0

1

0

Initial Value

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latches1
Latches
  • SR Latch

Q = Q0

Q = Q0

0

1

0

0

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latches2
Latches
  • SR Latch

Q = Q0

Q = 0

1

0

1

0

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latches3
Latches
  • SR Latch

Q = Q0

Q = 0

1

1

Q = 0

0

0

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latches4
Latches
  • SR Latch

Q = Q0

0

Q = 0

0

Q = 1

1

1

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latches5
Latches
  • SR Latch

Q = Q0

0

Q = 0

1

Q = 1

Q = 1

0

1

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latches6
Latches
  • SR Latch

Q = Q0

1

Q = 0

0

Q = 1

Q = Q’

1

0

1

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latches7
Latches
  • SR Latch

Q = Q0

1

Q = 0

1

0

Q = 1

Q = Q’

Q = Q’

0

1

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latches8
Latches
  • SR Latch

No change

Reset

Set

Invalid

Invalid

Set

Reset

No change

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latches9
Latches
  • SR Latch

No change

Reset

Set

Invalid

Invalid

Set

Reset

No change

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controlled latches
Controlled Latches
  • SR Latch with Control Input

No change

No change

Reset

Set

Invalid

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controlled latches1
Controlled Latches
  • D Latch (D = Data)

Timing Diagram

C

D

Q

t

Output may change

No change

Reset

Set

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controlled latches2
Controlled Latches
  • D Latch (D = Data)

Timing Diagram

C

D

Q

Output may change

No change

Reset

Set

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flip flops

C

CLK

Positive Edge

CLK

Negative Edge

Flip-Flops
  • Controlled latches are level-triggered
  • Flip-Flops are edge-triggered

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flip flops1

D Latch

(Master)

D Latch

(Slave)

D

D

C

Q

D

C

Q

Q

CLK

Flip-Flops
  • Master-Slave D Flip-Flop

Master

Slave

CLK

D

Looks like it is negative edge-triggered

QMaster

QSlave

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flip flops2

D

Q

Q

Q

D

Q

Flip-Flops
  • Edge-Triggered D Flip-Flop

Positive Edge

Negative Edge

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flip flops3

Q

J

Q

K

Flip-Flops
  • JK Flip-Flop

D=JQ’+K’Q

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flip flops4

T

D

Q

Q

Q

Q

Q

T

J

Q

T

K

Flip-Flops
  • T Flip-Flop

D=JQ’+K’Q

D=TQ’+T’Q=T Q

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flip flop characteristic tables

D

T

Q

Q

Q

Q

Q

J

Q

K

Flip-Flop Characteristic Tables

Reset

Set

No change

Reset

Set

Toggle

No change

Toggle

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flip flop characteristic equations

D

T

Q

Q

Q

Q

Q

J

Q

K

Flip-Flop Characteristic Equations

Q(t+1) =D

Q(t+1) =JQ’ + K’Q

Q(t+1) =TQ

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flip flop characteristic equations1

Q

J

Q

K

Flip-Flop Characteristic Equations
  • Analysis / Derivation

No change

Reset

Set

Toggle

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flip flop characteristic equations2

Q

J

Q

K

Flip-Flop Characteristic Equations
  • Analysis / Derivation

No change

Reset

Set

Toggle

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flip flop characteristic equations3

Q

J

Q

K

Flip-Flop Characteristic Equations
  • Analysis / Derivation

No change

Reset

Set

Toggle

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flip flop characteristic equations4

Q

J

Q

K

Flip-Flop Characteristic Equations
  • Analysis / Derivation

No change

Reset

Set

Toggle

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flip flop characteristic equations5

Q

J

Q

K

Flip-Flop Characteristic Equations
  • Analysis / Derivation

Q(t+1) =JQ’ + K’Q

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flip flops with direct inputs

Q

R

D

Q

Reset

Flip-Flops with Direct Inputs
  • Asynchronous Reset

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flip flops with direct inputs1

Q

R

D

Q

Reset

Flip-Flops with Direct Inputs
  • Asynchronous Reset

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flip flops with direct inputs2

PR

Q

D

Q

Preset

Reset

CLR

Flip-Flops with Direct Inputs
  • Asynchronous Preset and Clear

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flip flops with direct inputs3

PR

Q

D

Q

Preset

Reset

CLR

Flip-Flops with Direct Inputs
  • Asynchronous Preset and Clear

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flip flops with direct inputs4

PR

Q

D

Q

Preset

Reset

CLR

Flip-Flops with Direct Inputs
  • Asynchronous Preset and Clear

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analysis of clocked sequential circuits
Analysis of Clocked Sequential Circuits
  • The State
    • State = Values of all Flip-Flops

Example

AB= 0 0

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analysis of clocked sequential circuits1
Analysis of Clocked Sequential Circuits
  • State Equations

A(t+1)=DA

=A(t) x(t)+B(t) x(t)

=Ax + Bx

B(t+1)=DB

=A’(t) x(t)

=A’x

y(t)=[A(t)+ B(t)] x’(t)

=(A + B) x’

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analysis of clocked sequential circuits2
Analysis of Clocked Sequential Circuits
  • State Table (Transition Table)

0 00

0 10

0 01

1 10

0 01

1 00

0 01

1 00

A(t+1)=Ax + Bx

B(t+1)=A’x

y(t)=(A + B) x’

t

t+1

t

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analysis of clocked sequential circuits3
Analysis of Clocked Sequential Circuits
  • State Table (Transition Table)

t

t+1

t

A(t+1)=Ax + Bx

B(t+1)=A’x

y(t)=(A + B) x’

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analysis of clocked sequential circuits4
Analysis of Clocked Sequential Circuits
  • State Diagram

AB

input/output

0/0

1/0

0/1

0 0

1 0

0/1

1/0

0/1

1/0

0 1

1 1

1/0

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analysis of clocked sequential circuits5

D

Q

x

A

Q

y

CLK

Analysis of Clocked Sequential Circuits
  • D Flip-Flops

Example:

0

1

1

0

1

0

0

1

A(t+1)=DA =Ax y

01,10

0

1

00,11

00,11

01,10

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analysis of clocked sequential circuits6
Analysis of Clocked Sequential Circuits
  • JK Flip-Flops

Example:

0 0 1 0

0 0 0 1

1 1 1 0

1 0 0 1

0 0 1 1

0 0 0 0

1 1 1 1

1 0 0 0

0 1

0 0

1 1

1 0

1 1

1 0

0 0

1 1

JA = B KA = B x’

JB = x’ KB = A  x

A(t+1)=JA Q’A + K’A QA

= A’B + AB’ + Ax

B(t+1)=JB Q’B + K’B QB

= B’x’ + ABx + A’Bx’

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analysis of clocked sequential circuits7
Analysis of Clocked Sequential Circuits
  • JK Flip-Flops

Example:

0 0 1 0

0 0 0 1

1 1 1 0

1 0 0 1

0 0 1 1

0 0 0 0

1 1 1 1

1 0 0 0

0 1

0 0

1 1

1 0

1 1

1 0

0 0

1 1

1

0

1

1 1

0 0

0

0

0

0 1

1 0

1

1

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analysis of clocked sequential circuits8
Analysis of Clocked Sequential Circuits
  • T Flip-Flops

Example:

0 0

0 1

0 0

1 1

0 0

0 1

0 0

1 1

0

0

0

0

0

0

1

1

0 0

0 1

0 1

1 0

1 0

1 1

1 1

0 0

TA = B x TB = x

y = A B

A(t+1)=TA Q’A + T’A QA

= AB’ + Ax’ + A’Bx

B(t+1)=TB Q’B + T’B QB

= x  B

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analysis of clocked sequential circuits9
Analysis of Clocked Sequential Circuits
  • T Flip-Flops

Example:

0 0

0 1

0 0

1 1

0 0

0 1

0 0

1 1

0

0

0

0

0

0

1

1

0 0

0 1

0 1

1 0

1 0

1 1

1 1

0 0

0/0

0/0

0 0

0 1

1/0

1/1

1/0

1 1

1 0

0/1

0/0

1/0

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mealy and moore models
Mealy and Moore Models

The Mealy model: the outputs are functions of both the present state and inputs (Fig. 5-15).

The outputs may change if the inputs change during the clock pulse period.

The outputs may have momentary false values unless the inputs are synchronized with the clocks.

The Moore model: the outputs are functions of the present state only (Fig. 5-20).

The outputs are synchronous with the clocks.

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mealy and moore models1
Mealy and Moore Models

Fig. 5.21 Block diagram of Mealy and Moore state machine

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mealy and moore models2
Mealy and Moore Models

Mealy

Moore

For the same state,the output does not change with the input

For the same state,the outputchanges with the input

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moore state diagram
Moore State Diagram

State /Output

0

0

1

0 0 /0

0 1 / 0

1

1

1 1 / 1

1 0 / 0

1

0

0

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state reduction and assignment
State Reduction and Assignment

Fig. 5.25 State diagram

State ReductionReductions on the number of flip-flops and the number of gates.

  • A reduction in the number of states may result in a reduction in the number of flip-flops.
  • An example state diagram showing in Fig. 5.25.

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state reduction
State Reduction

Fig. 5.25 State diagram

  • Only the input-output sequences are important.
  • Two circuits are equivalent
    • Have identical outputs for all input sequences;
    • The number of states is not important.

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slide49

Equivalent states

  • Two states are said to be equivalent
    • For each member of the set of inputs, they give exactly the same output and send the circuit to the same state or to an equivalent state.
    • One of them can be removed.

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slide50

Reducing the state table

  • e = g (remove g);
  • d = f (remove f);

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slide51

The reduced finite state machine

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slide52

Fig. 5.26 Reduced State diagram

  • The checking of each pair of states for possible equivalence can be done systematically using Implication Table.
  • The unused states are treated as don't-care condition Þ fewer combinational gates.

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implication table
Implication Table
  • The state-reduction procedure for completelyspecified state tables is based on the algorithmthat two states in a state table can be combinedinto one if they can be shown to be equivalent.There are occasions when a pair of states do nothave the same next states, but, nonetheless, go toequivalent next states. Consider the followingstate table:
  • (a, b) imply (c, d) and (c, d) imply (a, b). Both pairsof states are equivalent; i.e., a and b areequivalent aswell as c and d.

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implication table1
Implication Table
  • The checking of each pair of states for possibleequivalence in a table with a large number ofstates can be done systematically by means of animplication table. This a chart that consists ofsquares, one for every possible pair of states, thatprovide spaces for listing any possible impliedstates. Consider the following state table:

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implication table2
Implication Table
  • The implication table is:

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implication table3
Implication Table
  • On the left side along the vertical are listed all thestates defined in the state table except the last,and across the bottom horizontally are listed all thestates except the last.
  • The states that are not equivalent are marked witha ‘x’ in the corresponding square, whereas theirequivalence is recorded with a ‘√’.
  • Some of the squares have entries of implied statesthat must be further investigated to determinewhether they are equivalent or not.
  • The step-by-step procedure of filling in the squaresis as follows:
    • Place a cross in any square corresponding to apair of states whose outputs are not equal forevery input.
    • Enter in the remaining squares the pairs ofstates that are implied by the pair of statesrepresenting the squares. We do that bystarting from the top square in the left columnand going down and then proceeding with thenext column to the right.

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implication table4
Implication Table

3. Make successive passes through the table todetermine whether anyadditional squaresshould be marked with a ‘x’. A square in thetable is crossed out if it contains at least oneimplied pair that is not equivalent.

4. Finally, all the squares that have no crossesare recorded with check marks. The equivalentstates are: (a, b), (d, e), (d, g), (e, g).

We now combine pairs of states into larger groupsof equivalent states. The last three pairs can becombined into a set of three equivalent states (d, e,g) because each one of the states in the group isequivalent to the other two. The final partition ofthese states consists of the equivalent states foundfrom the implication table, together with all theremaining states in the state table that are notequivalent to any other state:

(a, b) (c) (d, e, g) (f)

The reduced state table is:

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implication table5
Implication Table

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state assignment
State Assignment

State Assignment

To minimize the cost of the combinational circuits.

Three possible binary state assignments. (m states need n-bits, where 2n > m)

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slide60
Any binary number assignment is satisfactory as long as each state is assigned a unique number.

Use binary assignment 1.

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design procedure
Design Procedure

Design Procedure for sequential circuit

  • The word description of the circuit behavior to get a state diagram;
  • State reduction if necessary;
  • Assign binary values to the states;
  • Obtain the binary-coded state table;
  • Choose the type of flip-flops;
  • Derive the simplified flip-flop input equations and output equations;
  • Draw the logic diagram;

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design of clocked sequential circuits
Design of Clocked Sequential Circuits
  • Example:

Detect 3 or more consecutive 1’s

1

0

S0/0

S1/ 0

0

0

1

0

S3/ 1

S2/ 0

1

1

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design of clocked sequential circuits1

1

0

S0/0

S1/ 0

0

0

1

0

S3/ 1

S2/ 0

1

1

Design of Clocked Sequential Circuits
  • Example:

Detect 3 or more consecutive 1’s

0 00

0 10

0 00

1 00

0 00

1 10

0 01

1 11

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design of clocked sequential circuits2
Design of Clocked Sequential Circuits
  • Example:

Detect 3 or more consecutive 1’s

Synthesis usingDFlip-Flops

0 00

0 10

0 00

1 00

0 00

1 10

0 01

1 11

A(t+1)=DA (A,B, x)

= ∑ (3, 5, 7)

B(t+1)=DB (A,B, x)

= ∑ (1, 5, 7)

y(A,B, x) = ∑ (6, 7)

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design of clocked sequential circuits with d f f
Design of Clocked Sequential Circuits with D F.F.
  • Example:

Detect 3 or more consecutive 1’s

Synthesis usingDFlip-Flops

DA (A,B, x) =∑ (3, 5, 7)

= A x + B x

DB (A,B, x) = ∑ (1, 5, 7)

= A x + B’ x

y(A,B, x) = ∑ (6, 7)

= A B

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design of clocked sequential circuits with d f f1
Design of Clocked Sequential Circuits with D F.F.
  • Example:

Detect 3 or more consecutive 1’s

Synthesis usingDFlip-Flops

DA = A x + B x

DB = A x + B’ x

y = A B

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flip flop excitation tables
Flip-Flop Excitation Tables

0 0 (No change)

0 1 (Reset)

0

1

0

1

0 x

1 x

x 1

x 0

1 0 (Set)

1 1 (Toggle)

0 1 (Reset)

1 1 (Toggle)

0 0 (No change)

1 0 (Set)

0

1

1

0

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design of clocked sequential circuits with jk f f
Design of Clocked Sequential Circuits with JK F.F.
  • Example:

Detect 3 or more consecutive 1’s

Synthesis usingJKF.F.

JA (A,B, x) = ∑ (3)

dJA (A,B, x) = ∑ (4,5,6,7)

KA (A,B, x) = ∑ (4, 6)

dKA (A,B, x) = ∑ (0,1,2,3)

JB (A,B, x) = ∑ (1, 5)

dJB (A,B, x) = ∑ (2,3,6,7)

KB (A,B, x) = ∑ (2, 3, 6)

dKB (A,B, x) = ∑ (0,1,4,5)

0 x

1 x

x 1

x 1

0 x

1 x

x 1

x 0

0 x

0 x

0 x

1 x

x 1

x 0

x 1

x 0

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design of clocked sequential circuits with jk f f1
Design of Clocked Sequential Circuits with JK F.F.
  • Example:

Detect 3 or more consecutive 1’s

Synthesis usingJKFlip-Flops

JA =B x KA =x’

JB =x KB =A’ + x’

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design of clocked sequential circuits with t f f
Design of Clocked Sequential Circuits with T F.F.
  • Example:

Detect 3 or more consecutive 1’s

Synthesis usingTFlip-Flops

0

1

1

1

0

1

1

0

0

0

0

1

1

0

1

0

TA (A,B, x) = ∑ (3, 4, 6)

TB (A,B, x) = ∑ (1, 2, 3, 5, 6)

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design of clocked sequential circuits with t f f1
Design of Clocked Sequential Circuits with T F.F.
  • Example:

Detect 3 or more consecutive 1’s

Synthesis usingTFlip-Flops

TA =A x’+A’ B x

TB =A’ B +B x

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