Design and Implementation of VLSI Systems (EN1600S08) Lecture12: Logical Effort (1/2)

1. Design and Implementation of VLSI Systems (EN1600S08) Lecture12: Logical Effort (1/2) Prof. Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison Wesley – Rabaey/Pearson]

2. Impact of transistor sizing What happens to the delay if we increase the transistor sizes by K? Is it the case that increasing the size of the transistor always reduces delay?

3. Impact of sizing in a path ×K Cout Less output resistance; increase output capacitance → delay reduces (parasitic delay stays the same) Larger input capacitance → increases delay of previous stage! What is the final outcome? Should we size? By how much?

4. If you decide to increase everything by a factor of k Unloaded delay =3RC  12 ps in 180 nm process 40 ps in 0.6 mm process Impact of gate sizing How about an inverter?

5. Expressing delay as a linear model C is the capacitance of unit width transistor d = R/k(4h’C+ 6kC) d = RC(4h’/k + 6) effort delay parasitic delay Normalize with respect to 3RC (delay of unloaded inverter) d = 4/3 * h’/k + 2 logical effort (affected by gate type or geometry) electric effort

6. Summary of linear delay model • g: logical effort= ratio between input capacitance of the gate to the input capacitance of theinverter that would deliver the same current • h: electric effort = ratio between load capacitance and the gate input capacitance (sometimes called fanout) • p: parasitic delay • represents delay of gate driving no load • set by internal parasitic capacitance

7. Computing logical effort

8. Computing parasitic delay

9. Estimate the frequency of an N-stage ring oscillator Logical Effort: g = Electrical Effort: h = Parasitic Delay: p = Stage Delay: d = Frequency: fosc = Example: Ring oscillator

10. Example: Ring oscillator • Estimate the frequency of an N-stage ring oscillator Logical Effort: g = 1 Electrical Effort: h = 1 Parasitic Delay: p = 1 Stage Delay: d = 2 Frequency: fosc = 1/(2*N*d) = 1/4N 31 stage ring oscillator in 0.6 mm process has frequency of ~ 200 MHz

11. Estimate the delay of a fanout-of-4 (FO4) inverter Logical Effort: g = Electrical Effort: h = Parasitic Delay: p = Stage Delay: d = Example: FO4 Inverter

12. Estimate the delay of a fanout-of-4 (FO4) inverter Logical Effort: g = 1 Electrical Effort: h = 4 Parasitic Delay: p = 1 Stage Delay: d = 5 Example: FO4 Inverter The FO4 delay is about 200 ps in 0.6 mm process 60 ps in a 180 nm process f/3 ns in an fmm process