Exam 2 Review Two’s Complement Arithmetic Ripple carry ALU logic and performance - PowerPoint PPT Presentation

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Exam 2 Review Two’s Complement Arithmetic Ripple carry ALU logic and performance

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  1. Exam 2 Review • Two’s Complement Arithmetic • Ripple carry ALU logic and performance • Look-ahead techniques • Basic multiplication and division ( non- restoring) algorithms • IEEE 754 floating point standard (definition provided) • Write a sequence of register transfers to implement a given instruction for MIPS • Given a set of Register Transfers, design the control needed for some component

  2. State Register Transfers S0 M[PC] IR, PC + 4 PC, S1 S S1 R[IR[25-21]] A, R[IR[20-16]] B, PC + shlt2[sign_ext(IR[15-0])] ALUOut, (‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S9 S S2 A + sign_ext(IR[15-0]) ALUOut, ‘LW’S3 + ‘SW’S5 S S3 M[ ALUOut] MDR, S4 S S4 MDR R[ IR[20-16]], S0 S S5 B M[ ALUOut], S0 S S6 A op B ALUOut, S7 S S7 ALUOut R[IR[15-11]], S0 S S8 Zero PC + Zero ALUOut PC, S0 S S9 PC[31-28] : shlt2(IR[25-0]) PC, S0 S

  3. Next State Function with a Sequencer 16 Control Lines ROM PLA AddrCtl 1 STATE Adder Addr Select logic Op(5 –0) Looks like a Computer !

  4. Microprogramming • Define a symbolic set of microinstructions used to implement each instruction

  5. Microprogramming • Define a symbolic set of microinstructions used to implement each instruction • The microassembler will check for inconsistencies and convert to binary code

  6. Microprogramming • Define a symbolic set of microinstructions used to implement each instruction • The microassembler will check for inconsistencies and convert to binary code • Define independent fields to determine datapath control signals that must be asserted

  7. Microprogramming • Define a symbolic set of microinstructions used to implement each instruction • The microassembler will check for inconsistencies and convert to binary code • Define independent fields to determine datapath control signals that must be asserted • Define a field to determine the next state

  8. Microinstruction Design Label • Label controls microcode sequencing • Location of entry points • Used for sequencing • Value can be any string • Note: A numeric last character is special for • dispatching

  9. ALU Control IR MDR

  10. Microinstruction Design ALU Label control ALU control Add Subt Func – Use funct field of Op to define operation

  11. Microinstruction Design ALU Label control SRC1 SRC2 ALU control Add Subt Func – Use funct field of Op to define operation SRC1 # Select first ALU input PC A SRC2 # Select second ALU input B 4 Extend # sign extended (imm16) Extshft # shift left 2 [sign extended (imm16)]

  12. Register Control IR MDR

  13. Microinstruction Design ALU Register Label control SRC1 SRC2 control Register control Read # Read Reg(rs) into A, Reg(rt) into B Write ALU # Write ALUOut into Reg(rd) Write MDR # Write MDR into Reg(rt)

  14. Memory Control IR MDR

  15. Microinstruction Design ALU Register Label control SRC1 SRC2 control Memory Memory Read PC # Read M[PC] into IR ( and MDR) Read ALU # Read M[ALUOut] into MDR Write ALU # Write B into M[ALUOut]

  16. PCWrite Control IR MDR

  17. Microinstruction Design ALU Register PCWrite Label control SRC1 SRC2 control Memory control PCWrite control ALU # Load ALU result into PC ALUOut-cond # If Zero = 1, load ALUOut into PC Jump # Load jump address into PC

  18. Microinstruction Design ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Sequencing Seq # Go to next microinstruction in sequence Fetch # Go to microinstruction with Label “Fetch” Dispatch i # Dispatch with ROM i

  19. Microinstruction Design ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Sequencing Seq # Go to next microinstruction in sequence Fetch # Go to microinstruction with Label “Fetch” Dispatch i # Dispatch with ROM i See Summary Of Microcode Fields page C-29

  20. Basic steps all instructions execute • Access the Instruction from Memory • Decode Instruction and Access the Data • from Registers • 3. Perform the Instruction • 4. Write the Result

  21. State Register Transfers S0 M[PC] IR, PC + 4 PC, S1 S S1 R[IR[25-21]] A, R[IR[20-16]] B, PC + shlt2[sign_ext(IR[15-0])] ALUOut, (‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S9 S S2 A + sign_ext(IR[15-0]) ALUOut, ‘LW’S3 + ‘SW’S5 S S3 M[ ALUOut] MDR, S4 S S4 MDR R[ IR[20-16]], S0 S S5 B M[ ALUOut], S0 S S6 A op B ALUOut, S7 S S7 ALUOut R[IR[15-11]], S0 S S8 Zero PC + Zero ALUOut PC, S0 S S9 PC[31-28] : shlt2(IR[25-0]) PC, S0 S

  22. State Register Transfers S0 M[PC] IR, PC + 4 PC, S1 S ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch

  23. State Register Transfers S0 M[PC] IR, PC + 4 PC, S1 S ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add

  24. State Register Transfers S0 M[PC] IR, PC + 4 PC, S1 S ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4

  25. State Register Transfers S0 M[PC] IR, PC + 4 PC, S1 S ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC

  26. State Register Transfers S0 M[PC] IR, PC + 4 PC, S1 S ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU

  27. State Register Transfers S0 M[PC] IR, PC + 4 PC, S1 S ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq

  28. State Register Transfers S1 R[IR[25-21]] A, R[IR[20-16]] B, PC + shlt2[sign_ext(IR[15-0])] ALUOut, (‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S9 S ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq

  29. State Register Transfers S1 R[IR[25-21]] A, R[IR[20-16]] B, PC + shlt2[sign_ext(IR[15-0])] ALUOut, (‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S9 S ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq Add PC Extshft

  30. State Register Transfers S1 R[IR[25-21]] A, R[IR[20-16]] B, PC + shlt2[sign_ext(IR[15-0])] ALUOut, (‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S9 S ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read

  31. State Register Transfers S1 R[IR[25-21]] A, R[IR[20-16]] B, PC + shlt2[sign_ext(IR[15-0])] ALUOut, (‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S9 S ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1 Dispatch 1 Op Code Label lw or sw Mem1 R – type Rformat1 beq BEQ1 j JUMP1

  32. lw rt, imm16 (rs) or sw rt, imm16 ( rs) M[ R[rs] + sign_ext(imm16) ] R[rt] R[rt] M[ R[rs] + sign_ext(imm16) ] ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1 Mem1

  33. lw rt, imm16 (rs) or sw rt, imm16 ( rs) M[ R[rs] + sign_ext(imm16) ] R[rt] R[rt] M[ R[rs] + sign_ext(imm16) ] ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1 Mem1 Add A Extend Dispatch 2

  34. lw rt, imm16 (rs) or sw rt, imm16 ( rs) M[ R[rs] + sign_ext(imm16) ] R[rt] R[rt] M[ R[rs] + sign_ext(imm16) ] ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1 Mem1 Add A Extend Dispatch 2 LW2 Read ALU Seq Write MDR Fetch

  35. lw rt, imm16 (rs) or sw rt, imm16 ( rs) M[ R[rs] + sign_ext(imm16) ] R[rt] R[rt] M[ R[rs] + sign_ext(imm16) ] ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1 Mem1 Add A Extend Dispatch 2 LW2 Read ALU Seq Write MDR Fetch SW2 Write ALU Fetch

  36. R – Arithmetic – Logic Instruction op rd, rs, rt R[rs] op R[rt] R [rd] ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1 Rfmat1

  37. R – Arithmetic – Logic Instruction op rd, rs, rt R[rs] op R[rt] R [rd] ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1 Rfmat1 Func A B Seq

  38. R – Arithmetic – Logic Instruction op rd, rs, rt R[rs] op R[rt] R [rd] ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1 Rfmat1 Func A B Seq Write ALU Fetch

  39. beq rs, rt, imm16 I -type Zero =1 iff rs - rt = 0 Zero (PC+4) + Zero SUM[ (ShLt2[Sign_Ext(imm16)])+PC+4] PC ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1 BEQ1

  40. beq rs, rt, imm16 I -type Zero =1 iff rs - rt = 0 Zero (PC+4) + Zero SUM[ (ShLt2[Sign_Ext(imm16)])+PC+4] PC ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1 BEQ1 Subt A B

  41. beq rs, rt, imm16 I -type Zero =1 iff rs - rt = 0 Zero (PC+4) + Zero SUM[ (ShLt2[Sign_Ext(imm16)])+PC+4] PC ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1 BEQ1 Subt A B ALUOut-con Fetch

  42. j Label go to Label ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1 JUMP1 Jump Addr Fetch

  43. Microinstruction Design ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1 Mem1 Add A Extend Dispatch 2 LW2 Read ALU Seq Write MDR Fetch SW2 Write ALU Fetch Rfmat1 Func A B Seq Write ALU Fetch BEQ1 Subt A B ALUOut-con Fetch JUMP1 Jump Addr Fetch

  44. Implementing the microprogram • Each field in the microinstruction implies a set of control • signals to be asserted. See fig C.21 p.C-29

  45. Implementing the microprogram • Each field in the microinstruction implies a set of control • signals to be asserted. See fig C.21 p.C-29 • If a field that affects a state (memory) is blank, then no • control signal should be active.

  46. Implementing the microprogram • Each field in the microinstruction implies a set of control • signals to be asserted. See fig C.21 p.C-29 • If a field that affects a state (memory) is blank, then no • control signal should be active. • If a field that affects a mux or ALU operation is blank, • the output is not used, so it is a “don’t care”.

  47. Implementing the microprogram • Each field in the microinstruction implies a set of control • signals to be asserted. See fig C.21 p.C-29 • If a field that affects a state (memory) is blank, then no • control signal should be active. • If a field that affects a mux or ALU operation is blank, • the output is not used, so it is a “don’t care”. • The microcode assembler • 1. Converts the symbolic fields to a truth table for the • control signals [ microcode ] • 2. Resolves labels to addresses • 3. Builds the Dispatch ROM code

  48. Microprogram Assembler Microcode ROM Fabrication Control ROM

  49. Control ROM [Microcode] 16 Control Lines AddrCtl 1 Micro Counter Adder Addr Select logic Contains Dispatch ROM 1 Dispatch ROM 2 Op(5 –0)