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Chapter 11 Laboratory Experiment

Chapter 11 Laboratory Experiment. 11-0 Introduction to Experiments. 11-1 Binary and Decimal Numbers. 11-2 Digital Logic Gates. 11-3 Simplification of Boolean Functions. 11-4 Combinational Circuits. Chapter 11 Laboratory Experiment. 11-5 Code Converters.

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Chapter 11 Laboratory Experiment

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  1. Chapter 11 Laboratory Experiment 11-0 Introduction to Experiments 11-1 Binary and Decimal Numbers 11-2 Digital Logic Gates 11-3 Simplification of Boolean Functions 11-4 Combinational Circuits

  2. Chapter 11 Laboratory Experiment 11-5 Code Converters 11-6 Design with Multiplexers 11-7 Adders and Subtractors 11-8 Flip-Flops 11-9 Sequential Circuits

  3. Chapter 11 Laboratory Experiment 11-10 Counters 11-11 Shift Register 11-12 Serial Addition 11-13 Memory Unit 11-14 Lamp Handball

  4. Chapter 11 Laboratory Experiment 11-15 Clock Pulse Generator 11-16 Parallel Adder and Accumulator 11-17 Binary Multiplier 11-18 Asynchronous Sequential Circuits 11-19 Verilog HDL Simulation Experiment

  5. 11-0 Introduction to Experiments Experimental Equipment A logic breadboard must have : • LED indicator lamp • Toggle switches to provide logic-1 and -0 signals. • Pulsers with pushbutton and debounce circuits • A clock-pulse generator with at least two frequencies • A power supply of 5V. • Socket strips for mounting the ICs. • Solid hookup wire and a pair of wire strippers

  6. 11-0 Introduction to Experiments Experimental Equipment Additional equipment: • A dual-trace oscilloscope • A logic probe • A number of ICs.

  7. 11-0 Introduction to Experiments Series 7400

  8. 11-0 Introduction to Experiments Series 7400

  9. 11-0 Introduction to Experiments Physical Layout Ripple Counter IC 7493 Internal circuit diagram No connection

  10. 11-0 Introduction to Experiments Ripple Counter IC 7493 Schematic diagram When drawing schematic diagrams, the IC number is written insider the block. All input terminals are placed on the left of the block.

  11. 11-0 Introduction to Experiments Ripple Counter IC 7493 The letter symbols of the signals are written inside the block and the corresponding pin numbers are written along the external lines. All output terminals are placed on the right of the block.

  12. 11-1 Binary and Decimal Numbers Objectives • Introduces the breadboard to the students. • Acquaints the students with the cathode-ray oscilloscope. Reference Material Section 1-2 and 1-7

  13. 11-1 Binary and Decimal Numbers Binary Count Connect the IC to operate as a 4-bit binary counter by wiring the external terminals, as shown in the figure. All connections should be made with the power supply in the off position.

  14. 11-1 Binary and Decimal Numbers Oscilloscope Display Using a dual-trace oscilloscope, connect the output of the clock to one channel and the output of QA, to the second channel, followed by QB, QC, QD. Note that each flip-flop in turn divides its incoming frequency by 2.

  15. 11-1 Binary and Decimal Numbers BCD Count 0 1 When both R1 and R2 are equal to 1, all four cells in the counter clear to 0 irrespective of the input pulse. 0 1

  16. 11-1 Binary and Decimal Numbers Output Pattern Output QA produces a pattern of alternate 1's and 0's. Output QD produces a pattern of eight 0's followed by two 1's. Obtain the pattern for the other two outputs and check all four patterns on the oscilloscope. Connect the 7493 IC to count from 0000 to the following final counts: 0101, 0111, 1011

  17. 11-2 Digital Logic Gates Objectives: Investigate the logic behavior of various IC gate: 7400 Quadruple 2-input NAND gates 7402 Quadruple 2-input NOR gates 7404 Hex inverters 7408 Quadruple 2-input AND gates 7432 Quadruple 2-input OR gates 7486 Quadruple 2-input XOR gates

  18. 11-2 Digital Logic Gates Truth Table Use one gate from each IC and obtain the truth table of the gate. Waveforms For each gate, obtain the input-output waveform by observing the oscilloscope.

  19. 11-2 Digital Logic Gates Waveforms Obtain the input-output waveform relationship of the gate by observing the oscilloscope.

  20. 11-2 Digital Logic Gates Propagation Delay Connect all six inverters inside the 7404 IC in cascade. The output will be the same as the input except that it will be delayed. Using the oscilloscope, determine the delay from the input to the output of the sixth inverter.

  21. 11-2 Digital Logic Gates Universal NAND Gate Using a single 7400 IC, connect a circuit that produces • An inverter • A 2-input AND • A 2-input OR • A 2-input NOR • A 2-input XOR

  22. 11-2 Digital Logic Gates NAND Circuit Using a single 7400 IC, construct a circuit with NAND gates that implements the Boolean function F = AB + CD

  23. 11-3 Simplification of Boolean Functions Objectives: Acquaints the students with the relationship between a Boolean function and the corresponding logic diagram. Note: If an input to a NAND gate is not used, it should not be left open, instead, should be connected to another input that is used.

  24. 11-3 Simplification of Boolean Functions Logic Diagram

  25. 11-3 Simplification of Boolean Functions Logic Diagram implement the diagram and test the circuit by obtaining its truth table. Obtain the Boolean function of the circuit and simplify it using the map method. Construct the simplified circuit and test it.

  26. 11-3 Simplification of Boolean Functions Boolean Function implement the two functions together using a minimum number of NAND ICs. F1( A,B,C,D ) = (0,1,4,5,8,9,10,12,13) F2( A,B,C,D ) = (3,5,7,8,10,11,13,15)

  27. 11-3 Simplification of Boolean Functions Complement Plot the following Boolean function in a map: F = A'D + BD + B'C + AB'D Combine the 1's in the map to obtain the simplified function for F in sum of products. Then combine the 0's in the map to obtain the simplified function for F' also in sum of products.

  28. 11-4 Combinational Circuits Objectives Design, construct and test four combinational logic circuits. Reference Material Section 3-8 and 4-8

  29. 11-4 Combinational Circuits Design Example: Design a combinational circuit with four inputs—A,B,C, and D—and one output, F. F is to be equal to 1 when A = 1 provide that B = 0, or when B = 1 provided that either C or D is also equal to 1. Otherwise, the output is to be equal to 0.

  30. 11-4 Combinational Circuits Majority Logic: A majority logic is a digital circuit whose output is equal to 1 if the majority of the inputs are 1's. the output is 0 otherwise. Parity Generator: Design, construct, and test a circuit that generate an even parity bit from four message bits. Use XOR gates.

  31. 11-4 Combinational Circuits Decoder Implementation: Implement and test the combinational circuit using a 74155 decoder IC and external NAND gates. F1 = xy +x'y'z' F2 = x'y +xy'z' F3 = xy +x'y'z

  32. 11-5 Code Converters Objectives Design and construct three combinational-circuit converters. Reference Material Section 4-3

  33. 11-5 Code Converters Gray Code to Binary Design a combinational circuit that converts a four-bit Gray code number into the equivalent four-bit binary number. Implement the circuit with exclusive-OR gates. 9's complement Design a combinational circuit with four input lines that represent a decimal digit in BCD and four output lines that generate 9's complement of the input digit.

  34. 11-5 Code Converters Seven-Segment Display The 7447 IC is a BCD-to-seven-segment decoder/driver.

  35. 11-5 Code Converters Seven-Segment Display The 7730 seven-segment display contains the seven LED segments.

  36. 11-5 Code Converters Seven-Segment Display A 47Ω resistor to VCCis needed in order to supply the proper current to the selected LED segment.

  37. 11-6 Design with Multiplexers Objectives Design, construct a combinational circuit with multiplexers. Reference Material Section 4-10

  38. 11-6 Design with Multiplexers Multiplexer The diagram and function table of the multiplexer

  39. 11-6 Design with Multiplexers Design Specification A small corporation has 10 shares of stock, and each share entitles its owner to one vote at a stockholder's meeting. The 10 shares of stock are owned by four people as follows: Mr. W: 1 share Mr. X: 2 shares Mr. Y: 3 shares Mr. Z: 4 shares Design a circuit that displays the total number of shares that vote yes for each measure.

  40. 11-7 Adders and Subtractors Objectives Design, construct and test various adder and subtractor circuits. Reference Material Section 4-3, 4-7 and 4-13

  41. 11-7 Adders and Subtractors Half Adder Design, construct, and test a half-adder circuit using one XOR gate and two NAND gates. Full Adder Design, construct, and test a full-adder circuit using two ICs, 7486 and 7400.

  42. 11-7 Adders and Subtractors Parallel Adder IC type 7483 is a 4-bit binary parallel adder. Test it by connecting the four A inputs to a fixed binary number such as 1001 and the B inputs and input carry to five toggle switches.

  43. 11-7 Adders and Subtractors Adder-Subtractor The subtraction of two binary numbers can be done by taking the 2's complement of the subtrahend and adding it to the minuend.

  44. 11-7 Adders and Subtractors Adder-Subtractor When M=0, the bits of input B keep unchanged. The addition is performed.

  45. 11-7 Adders and Subtractors Adder-Subtractor When M=1, the XOR gates complement the bits of input B, and C0 is equal to 1. The subtraction is performed.

  46. 11-7 Adders and Subtractors Magnitude Comparator If S=0, A=B If C4=1, A >= B If C4=0, A < B If C4=1 and S<>0, A >B

  47. 11-8 Flip-Flops Objectives Construct, test and investigate the operation of various latches and flip-flops. Reference Material Section 5-2 and 5-3

  48. 11-8 Flip-Flops SR Latch Construct an SR latch with two cross-coupled NAND gates. Obtain the function table of the circuit.

  49. 11-8 Flip-Flops Master-Slave Flip-Flops Construct a Master-Slave Flip-Flops using two D latches and an inverter.

  50. 11-8 Flip-Flops Master-Slave Flip-Flops • Observe the waveform of the clock and the master and slave outputs. • Verify that the delay between the master and the slave outputs is equal to the positive half of the clock cycle. • Obtain a timing diagram

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