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16.482 / 16.561 Computer Architecture and Design

16.482 / 16.561 Computer Architecture and Design. Instructor: Dr. Michael Geiger Fall 2014 Lecture 5: Dynamic scheduling. Lecture outline. Announcements/reminders HW 4 due Monday, 10/6 HW 5 to be posted; due Friday, 10/10 Midterm exam: Thursday, 10/16

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16.482 / 16.561 Computer Architecture and Design

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  1. 16.482 / 16.561Computer Architecture and Design Instructor: Dr. Michael Geiger Fall 2014 Lecture 5: Dynamic scheduling

  2. Lecture outline • Announcements/reminders • HW 4 due Monday, 10/6 • HW 5 to be posted; due Friday, 10/10 • Midterm exam: Thursday, 10/16 • Will be allowed two double-sided 8.5” x 11” note sheets, calculator • Final exam: Thursday, 12/18, 6:30-9:30 PM • Review • Dynamic branch prediction • Today’s lecture • Dependences and hazards (review) • Dynamic scheduling Computer Architecture Lecture 5

  3. Review: Dynamic Branch Prediction • Want to avoid branch delays • Dynamic branch predictors: hardware to predict branch outcome (T/NT) in 1 cycle • Use branch history to determine predictions • Doesn’t calculate target • Branch history table: basic predictor • Which line of table should we use? • Use appropriate bits of PC to choose BHT entry • # index bits = log2(# BHT entries) • What’s prediction? • How does actual outcome affect next prediction? Computer Architecture Lecture 5

  4. T Predict Taken Predict Taken T NT NT NT Predict Not Taken Predict Not Taken T T NT Review: BHT • Solution: 2-bit scheme where change prediction only if get misprediction twice • Red: “stop” (branch not taken) • Green: “go” (branch taken) 11 10 01 00 Computer Architecture Lecture 5

  5. Review: Correlated predictors, BTB • Correlated branch predictors • Track both individual branches and overall program behavior (global history) • Makes some branches easier to predict • To make a prediction • Branch address chooses row • Global history chooses column • Once entry chosen, make prediction in same way as basic BHT (11/10  predict T, 00/01predict NT) • Branch target buffers • Save previously calculated branch targets • Use branch address to do fully associative search Computer Architecture Lecture 5

  6. Data Dependence and Hazards • InstrJ is data dependent (aka true dependence) on InstrI if: • InstrJ tries to read operand before InstrI writes it • or InstrJ is data dependent on InstrK which is dependent on InstrI • If two instructions are data dependent, they cannot execute simultaneously or be completely overlapped • If data dependence caused a hazard in pipeline, called a Read After Write (RAW) hazard I: add $1,$2,$3 J: sub $4,$1,$3 Computer Architecture Lecture 5

  7. ILP and Data Dependences,Hazards • HW/SW must preserve program order • Determined by source code • Implies data flow and calculation order • Therefore, dependences are a property of programs • Limits ILP • Dependence indicates potential hazard • Actual hazard and length of any stall is property of the pipeline • HW/SW goal: exploit parallelism by preserving program order only where it affects the outcome of the program Computer Architecture Lecture 5

  8. Name dependences • Name dependence: 2 instructions use same register or memory location, but no data flow between instructions associated with that name • Name dependences only cause problems if program order is changed • In-order program suffers no hazards from these dependences • Can be resolved through register renaming • Will revisit with dynamic scheduling Computer Architecture Lecture 5

  9. I: sub $4,$1,$3 J: add $1,$2,$3 K: mul $6,$1,$7 Name Dependence #1: Anti-dependence • Anti-dependence: InstrJ writes operand before InstrI reads it • If anti-dependence causes a hazard in the pipeline, called a Write After Read (WAR) hazard Computer Architecture Lecture 5

  10. I: sub $1,$4,$3 J: add $1,$2,$3 K: mul $6,$1,$7 Name Dependence #2: Output dependence • Output dependence: InstrJ writes operand before InstrI writes it. • If output dependence causes a hazard in the pipeline, called a Write After Write (WAW) hazard Computer Architecture Lecture 5

  11. Loop-carried dependences • Easy to identify dependences in basic blocks • Trickier across loop iterations • Example: L:add $t0, $t1, $t2 lw$t2, 0($t0) cmp $t2, $zero bne L • $t2 from lw used in next loop iteration • Loop-carried dependence: dependence in which value from one iteration used in another Computer Architecture Lecture 5

  12. Dependence example • Given the code below Loop: ADD $1, $2, $3 I0: ADD $3, $1, $5 I1: LW $6, 0($3) I2: LW $7, 4($3) I3: SUB $8, $7, $6 I4: DIV $7, $8, $1 I5: ADDI $4, $4, 1 I6: SW $8, 0($3) I7: SLTI $9, $4, 50 I8: BNEZ $9, Loop • List the data dependences • Assuming a 5-stage pipeline with no forwarding, which of these would cause RAW hazards? • List the anti-dependences • List the output dependences Computer Architecture Lecture 5

  13. Dependence example solution • Data dependences (RAW hazards underlined) $1: Loop  I0 $1: Loop  I4 $3: I0  I1 $3: I0  I2 $3: I0  I6 $6: I1  I3 $7: I2  I3 $8: I3  I4 $8: I3  I6 $4: I5  I7 $9: I7  I8 Computer Architecture Lecture 5

  14. Dependence example solution (cont.) • Anti-dependences $3: Loop  I0 $7: I3  I4 • Output dependences $7: I2  I4 Computer Architecture Lecture 5

  15. Realistic pipeline • A 5-stage pipeline is unrealistic for a modern microprocessor • Floating point (FP) ops take much more time than integer ops • Solution: Pipelined execution units • Allow integer ops (ADD, SUB, etc.) to finish in 1 cycle • Allow multiple FP ops of a particular type to execute at once • Example: in pipeline below, can have up to 4 ADD.D instructions at once • May also pipeline memory accesses (not shown below) Computer Architecture Lecture 5

  16. MIPS floating point • 32 SP floating point registers (F0-F31) • Registers paired for double precision ops • For example, in a double-precision add, “F0” refers to the register pair F0/F1 • Arithmetic instructions similar to integer • “.s” or “.d” at end of instruction for single/double • add.d, sub.d, mult.d, div.d • Data transfer • Load: L.S / L.D • Store: S.S / S.D Computer Architecture Lecture 5

  17. Latency and stalls • For our purposes, an instruction’s latency is equal to the number of pipeline stages in which that instruction does useful work • In the realistic pipeline slide: • Integer ops have a 1 cycle latency (EX) • Multiply ops have a 7 cycle latency (M1-M7) • FP adds have a 4 cycle latency (A1-A4) • Divide ops have a 24 cycle latency (D1-D24) • Memory ops have a 1+1 = 2 cycle latency • Address calculation in EX, memory access in MEM Computer Architecture Lecture 5

  18. Determining stalls • Most of the time, assuming forwarding: (# cycles between dependent instructions) = (latency of producing instruction – 1) • If no instructions between those dependent instructions, those cycles become stalls • Note: cycle that gets stalled is the cycle in which value is used Computer Architecture Lecture 5

  19. Case #1: ALU to ALU • Most common case: • Instruction produces result during EX stage(s) • Dependent instruction uses result in its own EX stage(s) • Easy to see stalls = (latency – 1) here • Note: same rule applies for ALU  load/store if ALU result is used for address calculation Computer Architecture Lecture 5

  20. Case #2: Load to ALU • Load produces result at end of memory stage • ALU op uses result at start of EX stage(s) • If you consider total latency (EX + MEM) for load, stalls = (latency – 1) Computer Architecture Lecture 5

  21. Case #3: ALU to store • Assumes ALU result is stored into memory • Appears only one stall is needed … • What’s problem? Computer Architecture Lecture 5

  22. Case #3: ALU to store (cont.) • Structural hazard on MEM/WB stages • Requires additional stall • Note that hazard shouldn’t exist • ADD.D doesn’t really use MEM stage • S.D doesn’t really use WB stage • Current pipeline forces us to share hardware; smarter design will alleviate this problem and reduce stalls Computer Architecture Lecture 5

  23. Case #4: Load to store • The one exception to the rule • Value loaded from memory; stored to new location • Used for memory copying • # stalls = (memory latency – 1) • Forwarding from one memory stage to the next • 0 cycles in our examples Computer Architecture Lecture 5

  24. Instruction add r3, r1, r2 mul r6, r4, r5 div r8, r6,r7 add r7, r1, r2 sub r8, r1, r2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 IF ID EX M WB IF ID E1 E2 E3 E4 E5 E6 E7 M WB IF ID x x x x x x E1 E2 E3 E4 … IF ID EX M WB IF ID EX M WB Out-of-order execution • Variable latencies make out-of-order execution desirable • How do we prevent WAR and WAW hazards? • How do we deal with variable latency? • Forwarding for RAW hazards harder Computer Architecture Lecture 5

  25. Advantages of Dynamic Scheduling • Dynamic scheduling: hardware rearranges instruction execution to reduce stalls while maintaining data flow and exception behavior • Benefits • Handles cases when dependences unknown at compile time • Allows processor to tolerate unpredictable delays (i.e., cache misses) by executing other code while waiting • Allows code that compiled for one pipeline to run efficiently on a different pipeline • Simplifies the compiler • Hardware speculation, a technique with significant performance advantages, builds on dynamic scheduling • Combination of dynamic scheduling and branch prediction Computer Architecture Lecture 5

  26. HW Schemes: Instruction Parallelism • Key idea: Allow instructions behind stall to proceedDIVD F0,F2,F4 ADDD F10,F0,F8SUBD F12,F8,F14 • Enables out-of-order execution and allows out-of-order completion(e.g., SUBD) • In a dynamically scheduled pipeline, all instructions still pass through issue stage in order (in-order issue) • Note: Dynamic execution creates WAR and WAW hazards and makes exceptions harder Computer Architecture Lecture 5

  27. Tomasulo’s Algorithm • Control & buffers distributed with Function Units (FU) • FU buffers called “reservation stations”; have pending operands • Registers in instructions replaced by values or pointers to reservation stations(RS) (register renaming) • Renaming avoids WAR, WAW hazards • More reservation stations than registers, so can do optimizations compilers can’t • Results to FU from RS, not through registers, over Common Data Bus that broadcasts results to all FUs • Avoids RAW hazards by executing an instruction only when its operands are available • Load and Stores treated as FUs with RSs as well • Integer instructions can go past branches (predict taken), allowing FP ops beyond basic block in FP queue Computer Architecture Lecture 5

  28. Tomasulo Organization FP Registers From Mem FP Op Queue Load Buffers Load1 Load2 Load3 Load4 Load5 Load6 Store Buffers Add1 Add2 Add3 Mult1 Mult2 Reservation Stations To Mem FP adders FP multipliers Common Data Bus (CDB) Computer Architecture Lecture 5

  29. Reservation Station Components • Op:Operation to perform in the unit (e.g., + or –) • Vj, Vk: Value of Source operands • Store buffers has V field, result to be stored • Qj, Qk: Reservation stations producing source registers (value to be written) • Note: Qj,Qk=0 => ready • Store buffers only have Qi for RS producing result • A: Address (memory operations only) • Busy: Indicates reservation station or FU is busy Computer Architecture Lecture 5

  30. Implementing Register Renaming • Register result status table • Indicates which instruction will write each register, if one exists • Holds name of reservation station with producing instruction • Blank when no pending instructions that will write that register • When instructions try to read register file, check this table first • If entry is empty, can read value from register file • If entry is full, read name of reservation station that holds producing instruction Computer Architecture Lecture 5

  31. Instruction execution in Tomasulo’s • Fetch: place instruction into Op Queue (IF) • Issue: get instruction from FP Op Queue (IS) • Find free reservation station (RS) • If RS free, check register result status and CDB for operands • If available, get operands • If not available, read new register name(s) and place in Qj / Qk • Rename result by setting appropriate field in register result status • Execute: operate on operands (EX) • Instruction starts when both operands ready and func. unit free • Checks common data bus (CDB) while waiting • We allow EX to start in same cycle operand is received • Number of EX (and MEM) cycles depends on latency Computer Architecture Lecture 5

  32. Instruction execution in Tomasulo’s • Memory access: only happens if needed! (MEM) • Write result: finish execution, send result (WB) • Broadcast result on CDB • Waiting instructions read value from CDB • Write to register file only if result is newest value for that register • Check register result status—see if RS names match • Assume only 1 CDB unless told otherwise • Potential structural hazard! • Oldest instruction should broadcast result first Computer Architecture Lecture 5

  33. Renaming example • Given the following available reservation stations: • Add1-Add4 (ADD.D/SUB.D) • Mult1-Mult2 (MULT.D/DIV.D) • Load1-Load2 (L.D) • Rewrite the code below with renamed registers, replacing register names with appropriate reservation stations. It may help to track the register result status for each instruction. L.DF2, 0(R1) ADD.D F0, F2, F6 SUB.D F6, F0, F2 MULT.D F2, F6, F0 DIV.D F6, F2, F6 S.D F6, 8(R1) Computer Architecture Lecture 5

  34. Solution • Assume reservation stations are assigned in order • Resulting code L.D Load1, 0(R1) ADD.D Add1, Load1, F6 SUB.D Add2, Add1, Load1 MULT.D Mult1, Add2, Add1 DIV.D Mult2, Mult1, Add2 S.D Mult2, 8(R1) Computer Architecture Lecture 5

  35. Tomasulo’s example • Assume the following latencies • 2 cycles (1 EX, 1 MEM) for memory operations • 3 cycles for FP add/subtract • 10 cycles for FP multiply • 40 cycles for FP divide • We’ll look at execution of the following code (solution to be posted separately) L.D F6, 32(R2) L.D F2, 44(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 ADD.D F6, F8, F2 Computer Architecture Lecture 5

  36. Dynamic loop unrolling • Why can Tomasulo’s overlap loop iterations? • Register renaming • Multiple iterations use different physical destinations for registers (dynamic loop unrolling). • Reservation stations • Permit instruction issue to advance past integer control flow operations • Also buffer old values of registers - totally avoiding the WAR stall Computer Architecture Lecture 5

  37. Tomasulo’s advantages • Distribution of the hazard detection logic • distributed reservation stations and the CDB • If multiple instructions waiting on single result, & each instruction has other operand, then instructions can be released simultaneously by broadcast on CDB • If a centralized register file were used, the units would have to read their results from the registers when register buses are available • Elimination of stalls for WAW and WAR hazards Computer Architecture Lecture 5

  38. Tomasulo Drawbacks • Complexity • Many associative stores (CDB) at high speed • Performance limited by Common Data Bus • Each CDB must go to multiple functional units  high capacitance, high wiring density • Number of functional units that can complete per cycle limited to one! • Multiple CDBs  more FU logic for parallel assoc stores • Non-precise interrupts! • We will address this later Computer Architecture Lecture 5

  39. Final notes • Next time: • Speculation • Midterm exam preview • Announcements/reminders • HW 4 due Monday, 10/6 • HW 5 to be posted; due Friday, 10/10 • Midterm exam: Thursday, 10/16 • Will be allowed two double-sided 8.5” x 11” note sheets, calculator • Final exam: Thursday, 12/18, 6:30-9:30 PM Computer Architecture Lecture 5

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