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Power PC Vs. MIPS

Power PC Vs. MIPS. By Saumil Shah and Joel Martin. Introduction. In 1991, a group from IBM, Motorola and Apple decided to design a new architecture, based on the existing IBM POWER architecture.

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Power PC Vs. MIPS

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  1. Power PC Vs. MIPS By Saumil Shah and Joel Martin

  2. Introduction • In 1991, a group from IBM, Motorola and Apple decided to design a new architecture, based on the existing IBM POWER architecture. • It was largely compatible with software written for the POWER, with some more troublesome instructions removed and emulated by the OS.

  3. Introduction • It added new instructions to replace removed ones, and improved the design of the memory system, and extended the design to 64-bit • The overall design of the PowerPC is very modular, with each CPU including the following:

  4. Overall Design • One or more Integer Execution Units: These are used for computations with integers and memory addresses. • One or more Floating Point Units: These are used for all computations with floating point values. It implements both 32-bit and 64-bit IEEE standard

  5. Overall Design • A single Branch Execution Unit: This unit is responsible for executing all conditional and unconditional branches, calls, system calls, and conditional move and logical operations. • One or more Storage Control Units: This unit handles access to main memory. As such, it contains the caches, virtual memory translation and the translation lookaside buffer.

  6. Power PC Architecture • PowerPC, being RISC, has all the advantages of many registers • 64-bit architecture • 32 integer and 32 floating point • and a simple easy to use instruction set • The multiple flag branching unit can lead to some complexity, but can also yield better performance

  7. Power PC Architecture • This architecture extends addressing and fixed point computation to 64 bits and supports dynamic switching between the 64-bit mode and 32-bit mode. • In 32-bit mode, a 64-bit Power PC processor will execute application binaries compiled for the 32-bit subset architecture.

  8. Basic Instructions Set

  9. Power PC Architecture • The designers of the Power architecture choose to minimize the time to complete a task. • The total time is the product of three components: path length, number of cycles needed to complete an instruction and cycle time. • Loads and stores account for the 20-30% of the instructions executed by most of the programs. • Many application manipulates array, for which the pattern of memory access is often regular (ex. Every nth element)

  10. Power PC Architecture • Based on these observations the designers included update forms of most load and store instruction. • The use of these instructions avoids the need of a separate address computation after each access

  11. Arithmetic Operations • While MIPS provide arithmetic operations such as Add, Subtract, etc… Power PC provides a lot more of those operations with correct precision. • The language processors for the PowerPC automatically use their chosen expression evaluation methods for the normal inline operators (+, -, *, /). All the arithmetic operations produce the best possible result: the mathematically exact result, coerced to the precision and range of the evaluation format.

  12. Power PC Architecture • Instructions were a fixed length (4 bytes) with consistent formats, permitting a simple instruction decoding mechanism • Load and store instructions provided all of the accesses to memory. • The architecture provided a set of general purpose registers (GPRs) for fixed-point computation, including the computation of memory addresses

  13. Power PC Architecture • It provided a separate set of floating-point registers (FPRs) for floating-point computation • It differed from other architecture like MIPS in that it was functionally partitioned, separating the functions of program flow control, fixed-point computation, and floating-point computation

  14. Power PC Architecture • Apart from the changes to the instruction set, the most significant changes were in the memory model and the memory management definition. • In the Power architecture, the processor did not maintain data memory consistent with either I/O accesses or instruction fetches. • Software had to manage memory consistency for both these areas. • Power processor always accessed main memory through caches.

  15. The PowerPC Calling Conventions • The native run-time environment on PowerPC processor-based Macintosh computers uses a set of uniform calling conventions: • Parameters are processed from left to right and are placed into general-purpose registers GPR3 through GPR10 and (when necessary) floating-point registers FPR1 through FPR13.

  16. Power PC Architecture

  17. The PowerPC Calling Conventions • Function results are returned in GPR3, FPR1, or by passing a pointer to a structure as the implicit leftmost parameter (as in the 680x0 C implementation). • Any parameters that do not fit into the designated registers are passed on the stack. In addition, enough space is allocated on the stack to hold all parameters, whether they are passed in registers or not.

  18. The Power PC Stack • Like the 680x0 run-time environment, the PowerPC run-time environment uses a grow-down stack that contains areas for a routine's parameters, for linkage information, and for local variables. • However, the organization of the stack in the PowerPC environment is significantly different from that in the 680x0 environment. • The PowerPC run-time environment uses a single stack pointer and no frame pointer. To achieve this simplification, the PowerPC stack has a much more rigidly defined structure.

  19. Power PC Stack

  20. Power PC Has lot more instruction set Has more branching capabilities Can do floating point operation Mips Has basic instruction set Has limited branching capabilites Comparing Power PC and Mips

  21. Summary • The Power PC Architecture permits a range of implementation from low cost controllers through high performance processors. • It allows the implementations of processors targeted for desktop and notebook systems, yet it contains features to support the efficient implementation of processors for use in a range of multiprocessor system.

  22. Basic similarities • They both use a pipelined architecture in their data path. • MIPS and Power PC both use a stack frame to store variables that are passed by various functions in memory starting in high memory and growing toward low memory. • They both support floating point operations. • They both are capable of supporting 32-bit register size.

  23. Continued Similarities • Both the Power PC and MIPS use a branch prediction unit to determine if a branch should be taken.

  24. Differences between Instruction sets • MIPS is not as elaborate meaning it does not support as many instructions as the Power PC architecture. • Even though they both support floating point operations, Power PC is more efficient in their functionality regarding floating point operations.

  25. Continued Differences • Power PC also uses a pipeline architecture that consists of seven pipelines as opposed to the five pipeline architecture we are using in MIPS. • Although it may not be as fast it is able to execute more instructions and can handle more hazards than the MIPS architecture. • Therefore, Power PC is a more efficient architecture.

  26. Continued Differences between MIPS and Power PC • A dynamically scheduled pipeline goes past stalls to find later instructions to be executed while waiting for the stall to be resolved. Therefore, the Power PC is more efficient in handling instruction hazards that would cause a stall in the pipeline. • Also the Power PC assembly language contains more jump instruction capabilities.

  27. Summary of the Power PC and MIPS • Even though both MIPS and Power PC are able to support 32-bit registers, the Power PC is also capable of supporting 64-bit registers as well. • Both support FLOPS or floating point operations, but the Power PC is able to support these operations faster. • They both have the basic instruction sets, but the Power PC is able to do more.

  28. Final Conclusion • Overall the Power PC is a better architecture than the MIPS architecture because it is capable of handling more instructions, it is able do more operations as far as branching and floating point operations and it is a more efficient architecture in handling various complexities in data and memory.

  29. Final Conclusion Continued • So if I had to choose between a MIPS architecture and a Power PC architecture, I would go with the Power PC because in overall performance it is better and is capable of doing more than the MIPS architecture can.

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