COMBINATIONAL LOGIC - 1

1. COMBINATIONAL LOGIC - 1

2. Overview

3. Combinational vs. Sequential Logic

4. At every point in time (except during the switching transients) each gate output is connected to either V or V via a low-resistive path. DD ss The outputs of the gates assumeat all timesthevalue of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. Static CMOS Circuit

5. Static CMOS

6. NMOS Transistors in Series/Parallel Connection • Transistors can be thought as a switch controlled by its gate signal • NMOS switch closes when switch control input is high

7. PMOS Transistors in Series/Parallel Connection

8. D D S S S S D D Pull-Up and Pull-Downwith NMOS and PMOS Pull-down: Pull-up:

9. Complementary CMOS Logic Style Construction

10. Example Gate: NAND

11. Example Gate: NOR

12. Example Gate: COMPLEX CMOS GATE

13. Cell Design • Standard Cells • General purpose logic • Can be synthesized • Same height, varying width • Datapath Cells • For regular, structured designs (arithmetic) • Includes some wiring in the cell • Fixed height and width

14. Standard Cell Layout Methodology – 1980s Routing channel VDD signals GND

15. Standard Cell Layout Methodology – 1990s Mirrored Cell No Routing channels VDD VDD M2 M3 GND Mirrored Cell GND

16. V DD Standard Cells N Well Cell height 12 metal tracks Metal track is approx. 3 + 3 Pitch = repetitive distance between objects Cell height is “12 pitch” Out In 2 Rails ~10 GND Cell boundary

17. V V DD DD Standard Cells With minimaldiffusionrouting With silicided diffusion Out In Out In GND GND

18. V DD Standard Cells 2-input NAND gate A B Out GND

19. V V DD DD Stick Diagrams Contains no dimensions Represents relative positions of transistors Inverter NAND2 Out Out In A B GND GND

20. Two Versions of C • (A + B) A C B A B C VDD VDD X X GND GND

21. X PUN C i VDD X B A j PDN GND Logic Graph Logic Graph A j C B X = C • (A + B) C i A B A B C

22. V DD PUN PUN B j C A X C i A B Euler Path & Consistent Euler Path X C i VDD X B A j A B C GND

23. OAI22 Logic Graph X PUN A C D C B D VDD X X = (A+B)•(C+D) C D B A A B PDN A GND B C D Consistent Euler Path

24. AOI22 Consistent Euler Path X X C C B B V V X X DD DD A A D D GND GND (a) Logic graphs for ( AB+CD ) (b) Euler Paths { a b c d } V DD x GND A B C D (c) stick diagram for ordering { } ABCD

25. Multi-Fingered Transistors One finger Two fingers (folded) Less diffusion capacitance

26. Properties of Complementary CMOS Gates • Full rail-to-rail swing; high noise margins • Logic levels not dependent upon the relative device sizes; ratioless • Always a path to Vdd or Gnd in steady state; low output impedance • Extremely high input resistance; nearly zero steady-state input current • No direct path steady state between power and ground; no static power dissipation • Propagation delay function of load capacitance and resistance of transistors

27. The Switch Model

28. VTC of Complementary CMOS Gates

29. Rp Rp A B Rn CL B Rn Cint A Analysis of Propagation Delay • Delay is dependent on the pattern of inputs • Low to high transition • both inputs go low • delay is 0.69 Rp/2 CL • one input goes low • delay is 0.69 Rp CL • High to low transition • both inputs go high • delay is 0.69 2Rn CL

30. Delay Dependence on Input Patterns A=B=10 A=1, B=1 0 Voltage [V] A=1 0, B=1 time [ps] Assumes worst case RPUP = RPDN NMOS = 0.5m/0.25 m  RPDN = 2 x [1/2 x Rn(Min)] PMOS = 0.75m/0.25 m  RPUP = 3 x [1/3 x Rn(Min)] CL = 100 fF

31. Rp Rp 2 2 Rp Rp B A B A Rn Cint Cint CL CL Rn Rn Rn B A B A 1 1 Transistor Sizing 4 4 2 2 Assumes Rp (min) = 2 x Rn(min)

32. B 8 12 A 4 6 C 8 12 D 4 6 OUT = D + A • (B + C) A 2 D 1 B 2 C 2 Transistor Sizing a Complex CMOS Gate • for symmetrical response (dc, ac) • for performance Assuming Rp(min) = 2Rn(min) Assuming Rp(min) = 3Rn(min) Focus on worst-case Input Dependent

33. A B C A B D C3 C2 C1 CL C D 4-input NAND Gate Vdd Out GND D A B C

34. A B D C B A C3 C2 C1 CL C D Fan-In Considerations Distributed RC model (Elmore delay) tpHL = 0.69 Reqn(C1+2C2+3C3+4CL) Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case.

35. tp as a Function of Fan-In and Fan-Out • Fan-in: quadratic due to increasing resistance and capacitance • Fan-out: each additional fan-out gate adds two gate capacitances to CL tp = a1FI + a2FI2 + a3FO

36. quadratic tpHL tp tpLH tp as a Function of Fan-In Gates with a fan-in greater than 4 should be avoided. tp (psec) tpLH fan-in

37. tp as a Function of Fan-Out All gates have the same drive current. tpNOR2 tpNAND2 tpINV tp (psec) Slope is a function of “driving strength” eff. fan-out

38. Propagation Delay Analysis (Example)

39. Numerical Examples for 0.25mm CMOS All NMOS: W = 0.5 m m, L = 0.25 m m R N = 13 k W /2 = 6.5 k W C1 = C2 = C3 = 0.85 fF CL(with FO = 1) = 3.2 fF t pHL = 0×69  (6.5 k W)(0.85 fF + 20.85 fF + 30.85 fF + 43.5 fF ) tpHL = 80ps

40. InN MN C3 C2 C1 CL In3 M3 In2 M2 In1 M1 Fast Complex Gates:Design Technique 1 • Transistor sizing • as long as fan-out capacitance dominates • Progressive sizing Distributed RC line M1 > M2 > M3 > … > MN (the fet closest to the output is the smallest) Can reduce delay by more than 20%; decreasing gains as technology shrinks

41. C2 C1 C1 C2 CL CL Fast Complex Gates:Design Technique 2 • Transistor ordering critical path critical path 01 charged charged 1 In1 In3 M3 M3 1 1 In2 In2 M2 discharged M2 charged 1 In3 discharged In1 charged M1 M1 01 delay determined by time to discharge CL, C1 and C2 delay determined by time to discharge CL

42. Transistor Sizing and Ordering

43. Fast Complex Gates:Design Technique 3 • Alternative logic structures F = ABCDEFGH

44. CL CL Fast Complex Gates:Design Technique 4 • Isolating fan-in from fan-out using buffer insertion

45. Fast Complex Gates:Design Technique 5 • Reducing the voltage swing • linear reduction in delay • also reduces power consumption • But the following gate is much slower! • Or requires use of “sense amplifiers” on the receiving end to restore the signal level (memory design) tpHL= 0.69 (3/4 (CL VDD)/ IDSATn ) = 0.69 (3/4 (CL Vswing)/ IDSATn )

46. V DD Example: Full Adder V DD B C A i A B A B C B in V DD A X C in C A in S C in V A B B DD A B A C in C B out Cout = Cin & (A | B) | (A & B) Sum= !Cout & (A | B | Cin) | (A & B & Cin) 28 transistors

47. B A B B A B Cin A A Cin !Cout !Sum Cin A Cin A B B A B Cin A B Static CMOS Full Adder Circuit !Sum= Cout & (!A | !B | !Cin) | (!A & !B & !Cin) !Cout = !Cin & (!A | !B) | (!A & !B) Cout = Cin & (A | B) | (A & B) Sum= !Cout & (A | B | Cin) | (A & B & Cin)

48. A Revised Adder Circuit

49. Project 1

50. Design of Clock Driver Network Goal: To reduce Energy/transition for the given timing constraints • · trise and tfall < 1000 psec • · tskew < 50 psec • The following design parameters • are also given: • · Vsupply = 2.5 V • trise and tfall of Clkin = 0.5 nsec • Tclk = 250 MHz • Use scmos.mod technology • Ignore wiring capacitance