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CFT/CPS readout & trigger overview

CFT/CPS readout & trigger overview. Fiber Tracker; Electronics. Tracking Electronics Analog Front End (AFE) boards 146 AFE’s exist (two kinds LHB, RHB) 73 RHBs @DØ; 73 LHB @ DØ or in mail Testing at DØ Water problems initially; solved One card gone through full testing

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CFT/CPS readout & trigger overview

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  1. CFT/CPS readout & trigger overview

  2. Fiber Tracker; Electronics • Tracking Electronics • Analog Front End (AFE) boards • 146 AFE’s exist (two kinds LHB, RHB) • 73 RHBs @DØ; 73 LHB @ DØ or in mail • Testing at DØ • Water problems initially; solved • One card gone through full testing • 36 cards thru phase 1,2 of 5 • Testing at SiDet, DAB and Lab 3 • More AFE boards • 50 more AFE PCB’s made for CPS and complete CFT stereo • 44 more AFE with modified VLPC bias distribution for FPS; layout complete • Expect all on site in 9 weeks

  3. Fiber Tracking Electronics • Tracking Electronics ( trigger part); cont’d • Mixer Boards ( need 20) • 2 prototypes fully operational • Production of 20 has started • Expect completion at start of October • Digital Front End (DFE) boards; need 40 • Have 20 installed • Other 20 exist, but need testing • Collector & Broadcasters • Have ordered CFT-A cards • Assembling orders for CPS & FPS Schedule for AFE: Complete central region during October shutdown; may request shorter access before that to install first 16.

  4. Trigger/DAQ Status Level 1 status Trigger systems: framework, LØ ( lum), tracker, calorimeter, muon

  5. Trigger/DAQ Status L2 overview S L I C L2MUO MUO L1MUO z-vertices (?) SMT STT refit tracks Matching of objects L2CFT CFT L1CFT L2 Global axial CPS stereo (u,v) L2CPS L2FPS Event-wide trigger decision FPS L1FPS CAL L1CAL L2CAL Critical path are: L2 Alpha’s. Have 9 “working” ones. Fabricating 12 more. Will have at most 9+12= 21 Preprocessor ( no inputs) with readout to L3 working. Need 16 for system; need 9 more for test setup

  6. L2Alpha status L2 cont’d • Assembly of 12 additional boards has started • 2 new prototype Alpha boards exist ( 1 DØ, 1 CDF) • Boards looked good on first inspection • DØ board not functioning ( trying to fix) • CDF board “flaky”: at DØ now for tests • ADCO ready to assembly the remaining 11 DØ boards upon approval of prototypes • Partial Alpha based Level 2 system available after Fall shutdown • The L2beta project prototype design started Part of Run 2b project

  7. o o o o o o o o o o o o L3 DAQ-FILTERING SCHEMATIC Infrastructure from Run I Front-End Digitizing Crates (2 of 16 groups) Data collection paths (16 total, ea. 48 Mbyte/s) VBD VBD o o o Readout Controller (VRC) (1 of 8) VRC VBD VBD o o o Primary Fiber Path (8 total, each 100 Mbyte/s) Ethernet Trigger data SB SB Event Tag Generator (ETG) SB Event tag path SB o o o Segment Controllers (SB) Processor Nodes (4 groups of 16) Filter Nodes (Linux) Switch

  8. Trigger/DAQ Status L3 status in words Original goals: • Built on existing infrastructure (VBD, data cables) for VME readout • Custom fast data path using PC’s with custom hardware in PCI slots  design SIB’s to do this. • Use NT operating system on all PC’s in this system • System and software implemented, but on emulators • Input rate into L3 of order 8 Hz (!!) • Only limited #filters ported to NT • NT support very difficult ( impossible) Status: Very slow development over last few months History Oversight & planning committees (CD) Decisions now: • Add a Linux based farm for filtering; only develop under Unix/Linux; no NT development. Orders out; strong team; will work by September • Accomplish ~100Hz by middle of August. • Several VRC’s are now operational • 1 VRC installed & running at DØ • Planning towards first complete hardware chain by Oct 15 and 1 kHz rate towards end of year. • Developing alternate solutions downstream and upstream of VRC. Move all under Technical Manager

  9. Backup slides

  10. Time scale & Milestones for Level 3 system August 13 Enough VRC’s ( 3 or 4) to realize 50-100Hz September 10 24 Level 3 noides will be at DØ September 24 Minimum of 24 SIB and 20 VBDI production boards available Replace initial VRC’s with these production versions October 15 One full vertical slice running reliably ( 10 hours running) Slice is: VRC + Segment Bridge+ L3 node with SIB Rate expected: 100Mbytes/sec ( ~ few 100Hz) October 29 Two full vertical slices running November 5 Two slices installed at DØ & running L3 Linux farm • farm nodes are ordered • Using 12 offline nodes now as teststand • Actively developing software • August 13: push data with 4 nodes; filter in 8 nodes • Burn in off real system in September

  11. CFT, CPS, FPS AFE 8 AFE 12 L1 Trig VLPC VLPC DAQ Fiber tracker readout front end system status * Increase # AFE8; decrease #AFE12 to minimally readout CFT, CPS. Delay FPS (AFE12).

  12. Alternate solution for Level 3 Assumes that the SIB1 i.e. VRC will work.

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