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Token Bit Manager for the CMS Pixel Readout. Edward Bartz Rutgers University. TBM for Phase I Upgrade Pixel Detector. 5 December 2013. L1 Trigger. Clock. TBM. TBM. Header -Trailer Output. +. CLK. L1. Token Out. Token In. ROC. ROC. ROC. 160Mb/s Output Data.

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token bit manager for the cms pixel readout
Token Bit Manager for the CMS Pixel Readout

Edward Bartz

Rutgers University

TBM for Phase I Upgrade Pixel Detector

5 December 2013

functions of the tbm

L1

Trigger

Clock

TBM

TBM

Header

-Trailer

Output

+

CLK

L1

Token Out

Token In

ROC

ROC

ROC

160Mb/s Output Data

Functions of the TBM
  • Distribute to Pixel Readout Chip’s (ROC)
    • L1 triggers
    • Clock
    • Register Programming
  • Controls readout through token pass
  • Write a Header and Trailer
    • Header/Trailer ID
    • Local Event Number
    • Status Information
  • Stack triggers awaiting token pass
    • 32 event deep
    • No readout after 16 deep
modifications from the present tbm
Modifications from the Present TBM
    • Remove Analog Encoded Digital Output Circuitry
  • Modify the Header/Trailer Circuitry
    • Add 160 MHz PLL
    • Modify State Machine (Header/Trailer are Shortened by 25ns)
    • Add 28 Bit Shift Register
  • Add Adjustable Token Out Timer to Truncate Large Events
  • Add a Temperature Measurement Circuit
  • Design Datakeeper to Combine two 160Mb/s Data Streams into one.
      • Add 400 MHz PLL.
      • Design Elastic buffer for shifting ROC data from 160 MHz to 400 MHz clock.
      • Design 4/5 Bit encoding with Non-Return to Zero Inversion.
      • Design a Framing Sequence for Front End Digitizer Alignment .
tbm08 testing

ROCs

ROCs

ROCs

ROCs

TBM08 Testing
  • Prototype Submitted January 2013
  • Issues found during testing.
    • Header/Trailer length variations.
      • State Machine skips counts..
    • 400MHz PLL radiation effects.
  • Irradiation Testing to be done soon.
  • Proposed Solutions
    • Improve Counter Timing
    • Improve TBM Core Clock (?)
    • Possibly make regulators software adjustable
    • Improve robustness of PLL

TBM08

DT

DT

DT

DT

160 Mb/s

160 Mb/s

160 Mb/s

160 Mb/s

DataKeeper

TBM

Header/Trailer

Shift Reg.

TBM

Header/Trailer

Shift Reg.

160 Mb/s

320 Mb/s

A

Multiplexer

Data

Encoder

400 Mb/s

B

Control

160MHz

PLL

400MHz

PLL

tbm09

ROCs

ROCs

ROCs

ROCs

TBM09

TBM09 (Modified TBM08)

160 Mb/s

160 Mb/s

320 Mb/s

320 Mb/s

A

A

Multiplexer

Multiplexer

Data

Encoder

Data

Encoder

400 Mb/s

400 Mb/s

B

B

160MHz

PLL

400MHz

PLL

160 Mb/s

160 Mb/s

TBM

Header/Trailer

Shift Reg.

TBM

Header/Trailer

Shift Reg.

next submission
Next Submission
    • Two possible options for the next submission
  • If the problem is well understood.
    • Submit production end of January 2014
    • Expect delivery end of March 2014
  • If the problem is not completely understood.
    • Submit end of March 2014 – Multiple variations of TBM on same wafer
    • Expect delivery end of May 2014
effects of logic voltage
Effects of Logic Voltage

Lowering TBM07a supply voltage to 1.5v does NOT cause the chip to misbehave.

tbm voltage regulators
TBM Voltage Regulators

TBM08

Core

Cap

Core

Periphery

Regulator

PLLs

a Core

Core

Regulator

Hub

b Core

DataKeeper

Mixer

clock distribution
Clock Distribution

Programming

Hub and

Control Registers

TBM Chip

Clock to

ROCs

Clock In

TBM Core

Header/Trailer

Counter

To allow the TBMs internal clock to compensate for capacitive loading of the clock line, and thereby align the TBM in time with the ROCs Clock

results
Results
  • Lowering just the core voltage on the TBM07a, causes it to misbehave exactly like the TBM08.
  • Lowering the just the periphery voltage of the TBM08 causes it to BEHAVE CORRECTLY.
  • This misbehavior is not effected by clock duty cycle (40/60 to 60/40).
  • This misbehavior is not effected by clock frequency (19MHz – 52MHz).
  • Conclusion – This problem is not completely a timing problem, but is caused by the difference between the two regulator output voltages.
  • 400MHz PLL
    • Maximum Frequency 460MHz (46MHz in clock)
    • Minimum Core voltage for 400MHz Locking – 1.92v
counter behavior
Counter Behavior

Triggers spaced 15 clocks apart (or less), Second token too early.

011111111100 TBM Header

00000011 Evt: 3

00000001 Flags: StackCount: 1

011111111000 ROC Header, ReadBackDataID: 0

011111111000 ROC Header, ReadBackDataID: 0

011111111111 TBM Trailer

00000000 Flags:

10000000 REG: 128

-- Note: No extra data between readouts

011111111100 TBM Header

00000100 Evt: 4

0000xxxx Flags: StackCount: x

011111111001 ROC Header, ReadBackDataID: 1

011111111001 ROC Header, ReadBackDataID: 1

011111111111 TBM Trailer

00000000 Flags:

11001100 REG: 204

Trigger

Token Out

Token Out

Triggers spaced 16 clocks apart. Second token in correct position.

011111111100 TBM Header

00000101Evt: 5

00000001 Flags: StackCount: 1

011111111000 ROC Header, ReadBackDataID: 0

011111111000 ROC Header, ReadBackDataID: 0

011111111111 TBM Trailer

00000000 Flags:

00000000REG: 0

-- Note: No extra data between readouts

011111111100 TBM Header

00000110Evt: 6

00000001 Flags: StackCount: 1

011111111001 ROC Header, ReadBackDataID: 1

011111111001 ROC Header, ReadBackDataID: 1

011111111111 TBM Trailer

00000000 Flags:

01000000 REG: 64

Trigger

Token Out

Token Out

data keeper core
Data Keeper Core

Frame

Permitted?

Next

4 Bits

Register

4 Bit

Shift

Register

4

TBM-B

Data

Encoded

Data Out

Latch Data

Every 2 Bits

160MHz

4 Bit

Shift

Register

Current

4 Bits

Register

Four To

Five Bit

Encoder

4

5 Bit

Shift

Register

Non-Return

to Zero

Inverted

TBM-A

Data

Encoded

Data Out

datakeeper encoding framing
DataKeeper Encoding/Framing

Replace this value with 11111 when preceded and followed by a 0

11011

Replace this value with 00000 when preceded and followed by a 1

00100

  • If we guarantee that the inverted channel is first, then this is the pattern sent when both TBMs are inactive.
encoding framing example
Encoding/Framing Example

0

1

1

1

0

1

1

1

1

0

1

1

Multiplexed

0

1

1

1

0

1

1

1

1

0

1

1

TBM A Out

Inverted

TBM B Out

0

1

0

0

0

0

0

1

1

0

1

1

1

0

0

0

Inverter

4 Bit Nibbles

TBM B Out

0

1

1

0

1

0

0

1

0

1

0

1

1

1

1

0

0

0

0

1

1

0

0

1

Final Encoded Data

0

0

B

1

2

2

A

A

Framing (Always done if A is followed by either 0,2,3,8-F)

1

0

1

1

0

1

0

1

1

0

1

1

1

0

1

1

1

1

0

1

0

0

1

0

1

1

1

1

1

0

0

1

0

0

1

0

1

0

0

0

If Instead The Nibbles Were:

The Final Encoded Data Would Be

No Framing, since A is followed by 1, Framing would result in 6 1s in a row

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