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Digital Integrated Circuits - week three -. Gheorghe M. Ş tefan http://arh.pub.ro/gstefan/ - 2014 -. BASIC CMOS CIRCUITS see Appendix: Basic circuits. Actual digital signals CMOS switches Gates: Inverter (NOT) NAND and NOR gates AND-NOR gates Many-input gates Tristate buffer

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digital integrated circuits week three

Digital Integrated Circuits- week three -

Gheorghe M. Ştefan

http://arh.pub.ro/gstefan/

- 2014 -

basic cmos circuits see appendix basic circuits
BASIC CMOS CIRCUITSsee Appendix: Basic circuits
  • Actual digital signals
  • CMOS switches
  • Gates:
    • Inverter (NOT)
    • NAND and NOR gates
    • AND-NOR gates
    • Many-input gates
    • Tristate buffer
    • Transmission gate
  • Flip-Flops

Digital Integrated Circuits - week three

actual signals
Actual signals

VDD evolved from 5V to 1V

VHmin = VLmax is impossible, because equality is impossible

VHmin > VLmax is a must

Digital Integrated Circuits - week three

forbidden region
Forbidden region

Digital Integrated Circuits - week three

noise margin
Noise margin

NM0 = VIL – VOL

NM1 = VOH - VIH

Digital Integrated Circuits - week three

cmos switches
CMOS switches

z : hi-impedance

Digital Integrated Circuits - week three

mos as switching device
MOS as switching device

CGS = COXLW

RON = 1/(n COX (W/L)(VGS – VT))

Digital Integrated Circuits - week three

not the inverter circuit
NOT: the inverter circuit

Static behavior

  • region A: X = 0
  • region B & C:

transition

  • region D: X = 1

Digital Integrated Circuits - week three

dynamic behavior
Dynamic behavior
  • tpHL: time from VOH to VOH/2
  • tpLH: time from 0 to VOH/2

Digital Integrated Circuits - week three

load capacitance c l
Load capacitance, CL

Load capacitance has three components:

  • The intrinsic capacitance of the driver inverter: parasitic drain/bulk capacitance, CDB
  • Wire capacitance: Cwire = Cthickox LwireWwire
  • Input capacitance of the receiver inverter:

CG = CGp + CGn = Cox(WpLp + WnLn)

CL = CDB + Cwire + CG

For long wires connecting the driver to receiver Cwire dominates the value of CL

Digital Integrated Circuits - week three

t phl discharging cl at the constant current i ds sat
tpHL: discharging CL at the constant current IDS(sat)
  • tr-: pMOS lin, nMOS cut
  • tr+: pMOS cut, nMOS sat
  • tr+ to (tr+tpHL): CL discharges at the constant current IDn(sat)

IDn(sat)=(nCox(Wn/Ln)(VOH –VTn)2)/2

dvout/dt =

-IDn(sat)/CL = (VOH /2 - VOH )/tpHL

tpHL = CL RONn(1/(1-(VTn/ VOH)))

tpHL = knCL RONn

tp = (tpHL + tpLH )/2

Digital Integrated Circuits - week three

buffering
Buffering

From tpHL/LH = kn/pCL RONn/p

tp = t0(Wload/Wdriver)

t0 is tpfor Wload=Wdriver

What is the solution for Wload >> Wdriver ?

tp(buffered) = tp0(W1/Wdriver + W2/W1 + Wload/W2)

Digital Integrated Circuits - week three

designing rule for buffering
Designing rule for buffering

The delay introduced by the new inverters must be minimal:

(W2/W1 + Wload/W2)’ = 0

W2 = (W1Wload)1/2

W2/W1 = Wload/W2= (Wload/W1 )1/2

The ratio of successive W must be constant

Example: let be Wload/Wdriver = n, then

W1/Wdriver = W2/W1 = Wload/W2 = n1/3

For n=1000, results the acceleration:

α = tp(no-buffer)/tp(buffered) = (n2)1/3/3 = 33.3

Digital Integrated Circuits - week three

power dissipation
Power dissipation
  • Switching energy: charging & discharging CL
  • Short-circuit energy: non-zero rise/fall times of the signal
  • Leakage current energy: important for L < 65nm

Digital Integrated Circuits - week three

switching power
Switching power

During each period, T, each capacitor

  • is charged to VDD through RONp with QL = CLVDD
  • is discharged to 0 through RONn

The energy to move QL from VDD to 0 is VDDQLthen:

pswitch = (VDD CL VDD)/T = CL V2DD fclock

Digital Integrated Circuits - week three

short circuit power
Short-circuit power

Depends on the saturation current

psc = IDD(mean) VDD

Digital Integrated Circuits - week three

the leakage current
The leakage current
  • Increase exponentially with temperature
  • Increases exponentially with reduction in VT
  • Dominated by the sub-threshold leakage

pleakage = IleakageVDD

Digital Integrated Circuits - week three

the nand gate
The NAND gate
  • For both input 1,

the output is 0

  • For at least one input 0

the output is 1

For n  1.7p, and Wn = Wp

What is the fastest transition?

What is the slowest transition?

Digital Integrated Circuits - week three

the nor gate
The NOR gate
  • For both input 0,

the output is 1

  • For at least one input 1

the output is 0

For n  1.7p, andWn = Wp

What is the fastest transition?

What is the slowest transition?

What do you prefer, NANDs or NORs?

Digital Integrated Circuits - week three

switching activity
Switching activity

Switching activity, σ, on the gate’s output depend on the logic function

pswitch = CL V2DD fclock => pswitch = σCL V2DD fclock

σ : probability of switching from 0 to 1

For 2-input AND:

σ = POUT-0 POUT-1 = (1-PAPB)PAPB

Conservative estimate for big systems: σ = 1/8.

Usually is measured: σ = 1/10

Digital Integrated Circuits - week three

glitching
Glitching

The activity to the output of a logic circuit depends also by the propagation time.

If ABC switches from

010 to 111

Then O2 does not change

according to the logic,

but it actually glitches.

Dangers:

  • The glitch can be latched
  • Increases the energy consumption

Digital Integrated Circuits - week three

many input gates
Many-input gates

tpmax(one-level) ~ 8×n×Cin tpmax(log-level) ~ 2×2×Cin + 2×n×Cin

Digital Integrated Circuits - week three

and nor gates
AND-NOR gates

Logic: depth = 3, size = 7

Electric: depth = 1, size = 4

Similar approach for:

(A + BC)’, (A(B+C))’, …

Digital Integrated Circuits - week three

home work 3
Home work 3

Problem 1: compute αforWload/Wdriver = 1000 when between driver NOT and load NOT 4 inverter circuits are inserted.

Problem 2: compute σ for a 2-input NOR gate and for a 2-input XOR gate.

Problem 3: draw, using 3 CMOS pairs, the circuit which performs the function (A(B+C))’.

Problem 4: design an asynchronously reset-able (RST) and preset-able (SET) DF-F.

(Problem 5: design a synchronously reset-able DF-F.)

Digital Integrated Circuits - week three

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