CMOS Digital Integrated Circuits

1. CMOS Digital Integrated Circuits Lec 7 CMOS Inverters: Dynamic Analysis and Design

2. CMOS Inverters – Dynamic Analysis and Design • Goals • Understand the detail dynamic analysis of the CMOS inverter. • Understand one set of design form CMOS equations. • Understand the basic CMOS design process using the CMOS static and CMOS design form dynamic equations.

3. CMOS Dynamic AnalysisCapacitance Model for CMOS VDD Cgs,p Csb,p Cdb,p Vin Vout Cgd,p Cgd,n FO Cdb,n Cint Cg Cgs,n Csb,n

4. CMOS Dynamic AnalysisCapacitance Model for CMOS • The aggregate capacitance driven by the output node of a CMOS inverter is in detail working from left to right, • Cload = Cinput + Cint + Cg in which Cinput= Cgd,n + Cgd,p + Cdb,n + Cdb,p(intrinsic component) Cint= interconnect capacitance Cg= thin-oxide capacitance over the gate area • (extrinsic component)

5. Vin idealized step input VOH V50% VOL t Vout VOH V50% VOL t t0 t1 t2 t3 Vout V90% V10% t tA tB tC tD CMOS Dynamic AnalysisDelay-Time Definitions V50% = VOL+(VOH-VOL)/2 . = (VOH+VOL)/2 τPHL = t1-t0 τPLH = t3-t2 τP = (τPHL+τPLH)/2 V10% = VOL+0.1(VOH-VOL) V90% = VOL+0.9(VOH-VOL) τfall = tB-tA τrise = tC-tD

6. CMOS Dynamic AnalysisDelay-Time Calculation (First Order Estimates) • The simplest approach of calculating the propagation delay is based on estimating the average capacitance current during charge down/up. where

7. iD,p iC Vin Vout iD,n Vout iD,n Vin Cload nMOS CMOS Dynamic AnalysisDelay-Time Calculation (More Accurate)(1/4) • The propagation delay can be found more accurately by solving the state equation of the output node. The current flowing through Cload is a function Vout as • τPHL: PMOS is off. The equivalent circuit during high-to-low output transition is

8. CMOS Dynamic AnalysisDelay-Time Calculation (2/4) The nMOS operates in two regions, saturation and linear, during the interval of τPHL. • Saturation Region iD,n=(kn/2)(Vin-VT,n)2=(kn/2)(VOH-VT,n)2 • Plug iD,n into Cload dVout/dt=-iD,n, and integrate both sides, we get t1’-t0 = 2CloadVT,n/[kn(VOH-VT,n)2] Vout VOH=VDD nMOS in saturation VOH -VT,n nMOS in linear region V50% t t0 t1’ t1

9. Vout VOH nMOS in saturation VOH -VT,n nMOS in linear region V50% t t0 t1’ t1 CMOS Dynamic AnalysisDelay-Time Calculation (3/4) • Linear Region iD,n= (kn/2)[2(Vin-VT,n)Vout-Vout2] = (kn/2)[2(VOH-VT,n)Vout-Vout2] • Plug iD,n into Cload dVout/dt=-iD,n, and integrate both sides, we have • Finally, since VOH=VDD and VOL=0, we have

10. VDD Vin pMOS iD,p Vout Cload CMOS Dynamic AnalysisDelay-Time Calculation (4/4) • τPLH: NMOS is off. The equivalent circuit during low-to-high output transition is With the similar way (t0→t1’→t1∕0→|VT,p|→V50%∕linear →saturation), we can have

11. CMOS Inverter Design • Design for Performance • Keep capacitance small • Increase transistor size • Watch out for self-loading! • IncreaseVDD(????)

12. 5.5 5 4.5 4 (normalized) 3.5 3 pHL τ 2.5 2 1.5 1 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 V (V) DD CMOS Inverter DesignDelay as a Function of VDD • VDD increases → τPHL/τPLH decreases. However, the power consumption also increases.

13. -11 x 10 3.8 (for fixed load) 3.6 3.4 3.2 (sec) 3.0 Self-loading effect: Intrinsic capacitances dominate p τ 2.8 2.6 2.4 2.2 2.0 2 4 6 8 10 12 14 S CMOS Inverter DesignDevice Sizing (1/5)

14. -11 x 10 5 PLH PHL 4.5 4 (sec) p P 3.5 3 1 1.5 2 2.5 3 3.5 4 4.5 5 R CMOS Inverter DesignDevice Sizing (2/5) • NMOS/PMOS Ratio R=Wp / Wn

15. CMOS Inverter DesignDevice Sizing (3/5) Self-Loading Effect Cload =Cgd,n(Wn) + Cgd,p(Wp) + Cdb,n(Wn) + Cdb,p(Wp) + Cint +Cg = f(Wn,Wp) • Using the junction capacitance expressions in Chapter 3, we have Cdb,n = (WnDdrain+xjDdrain)Cj0,nKeq,n+(Wn+2Ddrain)Cjsw,nKeq,n Cdp,n = (WpDdrain+xjDdrain)Cj0,pKeq,p+(Wp+2Ddrain)Cjsw,pKeq,p • Therefore, Cload can be rewritten as Cload= α0+ αnWn+ αpWp where 0 = Ddrain(2Cjsw,nKeq,n+2Cjsw,pKeq,p+xjCj0,nKeq,n+xjCj0,pKeq,p)+Cint+Cg n = Keq,n(Cj0,nDdrain+Cjsw,n) p = Keq,p(Cj0,pDdrain+Cjsw,p)

16. CMOS Inverter DesignDevice Sizing (4/5) • Therefore, τPHL and τPLH are • The ratio between the channel widths Wn and Wp is usually dictated by other design constraints such as noise margins and the logic inversion threshold. Let’s this transistor aspect ratio be defined as R ≡ Wp/Wn. Then, the propagation delay can be represented as

17. CMOS Inverter DesignDevice Sizing (5/5) • As we continue increase the values of Wn and Wp, the propagation delay will asymptotically approach a limit value for lager Wn and Wp, • The propagation delay times cannot be reduced beyond the above limits, and the limit is independent of the extrinsic capacitances.

18. 0.35 0.3 ) c e s n 0.25 ( L H p τ 0.2 0.15 0 0.2 0.4 0.6 0.8 1 τ (nsec) rise CMOS Inverter DesignImpact of Rise Time on Delay Propagation delay increases since both PMOS and NMOS are on during the charge-up and charge-down events.

19. CMOS Inverter DesignImpact of Channel Velocity Saturation • The drain current is linearly dependent onVGS Isat =κWn (VGS-VT) • Propagation delay only has a weak dependence on the supply voltage VDD

20. CMOS Dynamic AnalysisDynamic Power Dissipation (1/2) • The dynamic power dissipation can be derived as follows. Pdyn,avg = VDD IDD,avg • With IDD,avg taken over one clock period T. The capacitance current which equals the current from the power supply (assuming IDn = 0 during charging) is • Rearranging and integrating over one clock period T • Gives IDD,avg T = Cload VDD

21. CMOS Dynamic AnalysisDynamic Power Dissipation (2/2) • Solving for IDD,avg and substituting in Pavg: • It should be noted here the our simple Cload may underestimate the power dissipated. • In terms of SPICE simulation, the authors’ offer a circuit called power meter.