Digital Integrated Circuits for Communication

1. EveryWednesday: 15:00 hrs to 18:00 hrs هر اربع: شام 3 وڳي کان 6 وڳي تائين Digital Integrated Circuits for Communication احسان احمد عرساڻِي

2. My Introductionمنهنجو تعارف • Ahsan Ahmad Ursani • AssociateProfessor • Dept. of Telecommunication Engineering • Office No: TL-117 • Institute of Communication Technologies • Email: • Web page: • احسان احمد عرساڻي • ايسوسيئيٽ پروفيسر • شعبو ڏور ربطيات • دفتر نمبر: TL-117 • انسٽيٽيوٽ آف ڪميونيڪيشن ٽيڪنالاجيز • برق ٽپال: • ويب صفحو: ahsan.ursani@faculty.muet.edu.pk https://sites.google.com/a/faculty.muet.edu.pk/aau/home

3. The Teaching Planتدريسي رٿا Pre-Requisite: IC Design

4. The Textbookنصابي ڪتاب Digital Integrated Circuits A Design Perspective Jan M. Rabaey Chapter 6, 7, & 12

5. Chapter 2باب پهريون

6. Introduction

7. Timing Metrics for Sequential Circuits • Set-Up time tsu • Time beforeclock transition • Hold time thold • Time Afterclock transition • worst-case propagation delay tc-q • minimum delay (contamination delay) tcd • Propagation Delay of combinational logic tplogic • Time period of the Clock signal T

8. Timing Metrics for Sequential Circuits

10. Classification of Memory Elements • Foreground Memory • embedded into logic • organized as individual registers of register banks • Background Memory • Large amounts of centralized memory core • Not the subject of this chapter

11. Two types of memory Static Dynamic • Not refreshed frequently • Circuits with Positive feedback • Multivibrators • Refreshed frequently • In order of miliseconds • Store state of parasitic capacitances of MOS • Higher performance • Lower Power Dissipation

12. Latch • Level-sensitive circuit • Passes input D to the Output Q • Output does not change in the HOLD MODE • Input justbefore the goinginto HOLD phase isheld stable during the following HOLD phase • An essential component of Edge-triggeredRegister

13. The +ve and the –ve Latches

14. A Bistable Circuit • Basic Part of a memory • Havingtwo stable states • Use +ve feedback

15. The Bistability Principle

16. Metastability loop gain is greater than unity loop gain is much smaller than unity

17. Transition from one state to the other • This is generally done by applying a trigger pulse at Vi1 or Vi2 • The width of the trigger pulse need be only a little larger than the total propagation delay around the circuit loop, which is twice the average propagation delay of the inverters

18. SR Flip Flop

19. SR Flip-Flop Using NAND Gates Using NOR Gates

20. CMOS clocked SR flip-flop • Fully fully-complimentary CMOS implementation of SR flip Flop requires 8 transistors • Clocked operation will require extra transistors • Two Crossed Coupled Inverters • 4 extra transistors for R, S, and CLK inputs

21. CMOS clocked SR flip-flop • M4, M7, and M8 forms a ratioedInverter • Q is high and R is applied • we must succeed in bringing Q below the switching threshold of the inverter M1-M2 • Must increase the size of M5, M6, M7, and M8

22. Example 7.1: Transistor Sizing of Clocked SR Latch • (W/L)M1= (W/L)M3= 0.5mm/0.25mm • (W/L)M2 =(W/L)M4 =1.5mm/0.25mm • VM = VDD/2 • Q = 0 • VOL (Q=0) < VM • (W/L)M5-6≥ 2.26 • (W/L)M5 = (W/L)M6 ≥ 4.5

23. DC output voltage vs. individual pulldowndevice TransientResponse

24. Example 7.2: Propagation Delay of Static SR Flip-Flop

25. Problem 7.2 Complimentary CMOS SR FF • Instead of using the modified SR FF of Figure 7.8, it is also possible to use complementary logic to implement the clocked SR FF. Derive the transistor schematic (which consists of 12 transistors). This circuit is more complex, but switches faster and consumes less switching power. Explain why.

26. Multiplexer-Based Latches

27. Multiplexer-Based Latches Advantages Disadvantages • The feedback loopis off while output ischanging • Feedback is not to beoverridden to change the output • Transistor sizingis not critical to fuctionality • Clockloadis 4

28. NMOS latch using Pass Transistors • Clockload = 2 • Degradedlogic 1 passed to the first inverter (VDD-VTN) • For smaller values of VDD • Less noise margin • Lessswitching performance • Static Power Dissipation

29. Master Slave Edge-triggered Register:Positive edge-triggered

30. Problem 7.3: Optimization of the Master Slave Register • I1 and I2canberemoved • Functionalityaffected ?

31. Timing properties of Multiplexer-based Master-Slave Register • Set-up time • Hold time • Propagation Delay • Propagation Delay of Inverter (tpd_inv) • Propagation Delay of TransmisionGate (tpd_tx) • tsu= 3 tpd_inv + tpd_tx • tc-q = tpd_tx(T3) + tpd_inv(I6) • thold = 0

32. Master Slave Edge-triggered Register:NegativeEdge-trggerred • Draw a circuit based on transmission gatemultiplexers

33. Set-up time simulation in SPICE • Progressively skew the input with respect to the clock edge until the circuit fails

34. Set-up time simulation Tsetup = 0.21 nsec Tsetup = 0.20 nsec

35. Simulation of propagation delay • Tc-q = tpd_tx(T3) + tpd_inv(I6) • Tc-q(LH) = 160 ps • Tc-q(HL) = 180 ps

36. ReducedClockLoad • Feedback transmission gatesremoved • Clockload = 4 • RatioedLogic • T1shouldbeproperlysizedso as to be able to change the I1I2 state

37. Reverse Conduction • T2canalso drive T1 • I4 must be a weakdevice to preventitfromdriving T2

38. Non IdealClockSignals • Assumptionthatclock inversion takes ZERO time • Effects of Capacitive loadsdissimilar capacitive loads due to different data stored in the connectinglatches • Differentrouting conditions of the twosignals • ClockSkew

39. Problems due to ClockSkew • Direct Path B/W D and Q • Race Condition • Can conduct on +veedge of clock

40. Solution to ClockSkew: Pseudostatic2-phase D register • Two phase Clock signal • 2 non-overlaping phases

41. Dynamic Transmission GateEdgetriggeredRegister • tsu= tpinv • tcq= 2tpinv + tptgate • NeedsRefereshing • ClockOverlapcan cause the problemcalled Race • 1-1 Overlap • Increasinghold time • 0-0 Overlap • Toverlap0-0 < tT1+ tI1+ tT2 • Input Signal D must not be able to propagate through T2 During 0-0 o overlap

43. C2MOS – Clocked CMOSA ClockSkewInsensitiveApproach • Positive EdgeTriggered Master –Slave Register • Clocked CMOS • CLK=0; Master samples the inverted version of D on X • CLK=1; Master is in the HOLD mode and Slave passes the value on X to Q

44. 0 – 0 Overlap 0 – 0 Overlap

45. 1 – 1 Overlap 1 – 1 Overlap

46. C2MOS – Clock Overlap • 0 – 0 overlap does not create any problem • 1 – 1 overlap puts a HOLD constraint

47. Dual EdgeRegisters • It consists of two parallel masterslavebased edge-triggered registers, whose outputs are multiplexed using the tri-state drivers • The advantage of this scheme is that a lower frequency clock (half of the original rate) is distributed for the same functional throughput, resulting in power savings in the clock distribution network

48. True Single-Phase Clocked Register (TSPCR) Positive Latch Negative Latch

49. Embedded logic

50. Example 7.4 Impact of embedding logic into latches on performance • Consider embedding an AND gate into the TSPC latch, as shown in Figure 7.31b. In a 0.25 • mm, the set-up time of such a circuit using minimum-size devices is 140 psec. A conventional • approach, composed of an AND gate followed by a positive latch has an effective set-up time • of 600 psec (we treat the AND plus latch as a black box that performs both functions). The • embedded logic approach hence results in significant performance improvements.