Lab 4 UART Transmitter

1. Lab 4UART Transmitter BYU ECEn 320

2. A1 Expansion Connector A2 Expansion Connector VGA B1 Expansion Connector Power Serial PS2 UART Transmimtter Specification Send ASCII value on 8 toggle switches to serial port for display on screen when button 1 is pressed. BYU ECEn 320

3. Top Level System Block Diagram Clock/Reset GeneratorSwitch and Button InterfaceButton Debouncer Two Entities: tx_test - top level file to test the transmitter tx - The transmitter itself, which is instantiated in the body of tx_test You will reuse the transmitter in a later lab tx_test 7 segment display ctrl tx Transmitter BYU ECEn 320

4. Transmitter Tester (tx_test)Block Diagram tx clk_in clk (50 MHz) rst tx_busy Debounce Circuit tx_out send_character txd button 8 data_in display cntrl signals switch(7 downto 0) BYU ECEn 320

5. Transmitter (tx) Block Diagram clk rst Shift Register data_in 8 Transmit Out tx_out shift_out shift FSM load send_character stop start clkrst BitTimer clk rst tx_busy tx_bit clrTimer BYU ECEn 320

6. Bit Timer clk rst Shift Register data_in 8 Transmit Out tx_out shift_out shift FSM load send_character stop start clkrst BitTimer clk rst tx_busy tx_bit clrTimer BYU ECEn 320

7. Bit Timer - Transmitter Clocking • Everything is clocked on same global clock (clk) • Global clock is 50MHz • The Bit Timer controls the timing of bits coming out of the serial port. • Bit Timer needs to create timing pulse at rate of 19,200Hz • That is the baud rate of our serial port • Divide factor = 50,000,000/19,200 = 2604.1666… • We will use 2604 cycles/pulse BYU ECEn 320

8. Transmitter Bit Timer • Bit timer can be created from a counter • Can be cleared, otherwise increments up to 2603 and rolls over • Signal tx_bit is asserted during the last cycle (cycle 2603 in this case) clk tx_bit 2604 cycles state serial_out “one bit” BYU ECEn 320

9. Building a Parameterizable Bit-Timer • To make our transmitter more reusable, we will use generics for the clock rate and baud rate generic CLK_RATE : Natural := 50_000_000; generic BAUD_RATE : Natural := 19_200; generic BIT_TIMER_WIDTH : Natural := 12; . . . constant BIT_TIMER_COUNT : Natural := CLK_RATE/BAUD_RATE; signal BIT_TIMER : unsigned(BIT_TIMER_WIDTH-1 downto 0); • Use the constant BIT_TIMER_COUNT in the design of your counter to determine when to return to 0 • Changes in generics will automatically result in changes to the counter BYU ECEn 320

10. Shift Register clk rst Shift Register data_in 8 Transmit Out tx_out shift_out shift FSM load send_character stop start clkrst BitTimer clk rst tx_busy tx_bit clrTimer BYU ECEn 320

11. Shift Register • A shift register is used to load the “parallel” data from the switches and “shift” the data out on the serial port • The “LSB” of the shift register drives the “shift_out” signal • load: The shift register should load all data from the switches • shift: The shift register should shift right BYU ECEn 320

12. Transmit Out clk rst Shift Register data_in 8 Transmit Out tx_out shift_out shift FSM load send_character stop start clkrst BitTimer clk rst tx_busy tx_bit clrTimer BYU ECEn 320

13. Transmit Out • Additional logic is needed to make sure the TX signal is valid and clean • Outputs a ‘0’ when start is high • Outputs a ‘1’ when stop is high • Outputs selected data bit from shift_outotherwise • This signal should be registered in a flip-flop to prevent glitches before leaving the chip • The Flip-Flop will remove any transient glitches. BYU ECEn 320

14. Transmitter FSM clk rst Shift Register data_in 8 Transmit Out tx_out shift_out shift FSM load send_character stop start clkrst BitTimer clk rst tx_busy tx_bit clrTimer BYU ECEn 320

15. Transmitter FSM • Controls the operation of all elements in the transmitter • Controls clearing of Bit timer • Controls loading and shifting of shift register • Controls transmit out (start bit, stop bit, or shift bit) • Inputs: • send_character: Control signal to initiate transfer • tx_bit: Indicates the end of a bit time • Outputs: • tx_busy: Transmitter is busy (middle of transmit) • clrTimer: Clear the bit timer • load: Load switch data into shift register • shift: Shift shift register • stop: Send a stop bit • start: Send a start bit BYU ECEn 320

16. Transmitter State Diagram (Transitions) send_character send_character rst send_character IDLE RETRN send_character tx_bit See following two pages for a description of the states and the state machine outputs STRT tx_bit STP tx_bit tx_bit tx_bit tx_bit tx_bit tx_bit tx_bit tx_bit tx_bit tx_bit B7 B6 B5 B4 B3 B2 B1 B0 tx_bit tx_bit tx_bit tx_bit tx_bit tx_bit tx_bit tx_bit BYU ECEn 320

17. Transmitter FSM States • IDLE: Waiting for signal to start transmit • STRT: Issue start bit • B0-B7: Send a bit (B0 = send bit 0, etc.) • STP: Send stop bit • RETRN: Wait for “send_character” to clear BYU ECEn 320

18. Transmitter FSM Outputs • tx_busy: • true when not in IDLE state • load: • Occurs on transition from IDLE state to STRT state • STATE = IDLE and (send_character = ‘1’) • shift: • Occurs on each transition between Bx and Bx+1 • tx_bit = ‘1’ and (STATE = B0 or STATE = B1 . . . or STATE = B7) • stop: • True when in STP, RETRN, and IDLE state • Transmitter must drive a ‘1’ when IDLE (i.e. a STOP bit) • start: • True in STRT state • clrTimer: • True in IDLE state (the counter is free running otherwise) BYU ECEn 320

19. Signal Debouncing BYU ECEn 320

20. Signal Bouncing • The buttons will “bounce” many times each time the button is pressed • Pressing the button generates a very noisy analog signal • The corresponding digital signal will transition many times until the button settles • Additional circuitry must be added to “debounce” the button • If this bounce is not removed, one press of the “send character” button will result in many distinct send character signals • You will see many characters send to the PC • You must add a debouncing circuit to this signal BYU ECEn 320

21. Button Debounce Circuit button settle time is typically around 10 msec switch settle time switch settle time buttoninput DebounceLogic output A digital equivalent of a low pass filter BYU ECEn 320

22. Debounce Circuit Timer/Clock Divider clk en_sample Tsample > Tsettle D Q en bouncy debounced clk en_sample Tsample bouncy Tsettle debounced BYU ECEn 320

23. Debounce Circuit • You can create a debouncer by “sampling” the input signal infrequently (~10 ms?) • Create a counter to measure the delay time • Sample the input signal every time the counter rolls over • You should make the delay parameterizable (with generics) so you can adjust the debounce time BYU ECEn 320