ASMD based Design: UART Transmitter

1. ASMD based Design: UART Transmitter

2. Agenda of Lecture • UART Basics • Design Partitioning of UART TX • Control Unit and Its ASMD • UART TX, Putting it All Together Purpose of this Lecture is not to go through UART or To learn it. Infact this Lecture is insight of ASMD based designs, how you can think a design, Draw the ASMD and Write the code of the ASMD. Take this Lecture as thinking Point of ASMD designs.

3. 1- UART Basics • UART (Universal Asynchronous Receiver Transmitter) Performs serial communication between UART and other components. • UART takes a Byte of Data in Parallel converts it into serial form and includes Stop, Start and Parity Bits with the data. • The UART transmission is controlled by the Clock specially controlled with accordance to the Baud Rate.

4. Serial Communication

5. Steps for ASMD design Methodology • Draw a Block Diagram of the Design given on Side 6. • Partition the design into control unit and Data Path as on Slide-6. Connect all inputs to Control unit and all output to Data Path. • Start thinking about possible components in the Data path and Signals associated with them. • Figure out Control Signals from the Data Path Signals. • Plan States of Control Unit and Draw its ASMD of the Control Unit.

6. 2- Design Partitioning of UART TX Partition the design into Control Unit and Data Path Connect all inputs to the Control Unit and out puts to Data Path.

7. Possible Data Path components • A 8-Bit register needed to buffer the data. • A Counter which can count from 0 to 9. When the counter will complete its counting cycle this will ensure that Serial data has been transmitted. • A shift register which can shift the bit out one by on each transact of the Clock. • A parity calculator which generates one bit parity when the 8-bit data is given to it.

8. Possible Data Path components

9. Possible Data Path components

10. Connecting Data path and Control Unit

11. 3- Control Unit Design • RST_TXReg, RST Counter and RST_Dregcan reset the respective components. • LD_Dregenables loading data into Data_Reg. • LD_TxRegwill load parity Data, Data from Data_Reg . • Shift_TxReg Will control Shifting operation of Tx_Reg.

12. ASMD of Control Unit

13. Simulation of Control Unit

14. 4-UART Transmitter: Putting it All Together • The host Initially send data on Data_In and assert Data_Ready to tell UART_TX the new data is available. • The Data Loaded by Host will remain in Buffer of UART_TX unit Data_Send is not asserted. Host raise Data_Send to Tell UART Transmitter to send data out one by one.

15. UART Transmitter Working, Loading Data • The Host Loads the Data by giving data in Data_In and Asserting Data_Ready Signal. • The Control Unit Generate LD_Dreg, Data path loads data seeing this signal.

16. UART Transmitter Working, Ready to Transmit • The Host Asserts Data_Send to tell Design to Send the Data now. • Control Unit Asserts LD_TxReg after seeing Data_Send. This signal loads Data from Data_Reg into TX_Reg and Parity from Pout.

17. UART Transmitter, Transmitting • In the Next Clock Cycle Shift_TxReg is asserted by Control Unit. This Enable counter. • The first bit of TX_Reg becomes one which is tied to the output. This send Start bit.

18. UART Transmitter, Transmitting • On each Clock Cycle TX_Reg is shifted one by one insert 1 from Left hand side. Bit by Bit 8 Clock Cycles send all the data serially out. • Cflag of Counter is raised when counter counts 9. At this time all the bits are transmitted. And Shift_TxReg is deasserted.

19. UARTTransmitter,Simulation