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A Rad-Hard Slow Control Network for the CMS Central Tracker

A Rad-Hard Slow Control Network for the CMS Central Tracker. A. Marchioro, G. Cervelli, F. Faccio, K. Kloukinas, C. Ljuslin, P. Moreira, E. Murer, C. Paillard, F. Vasey CERN-EP. Outline. Motivations and Requirements Architecture Network and system components: Token-Ring Network

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A Rad-Hard Slow Control Network for the CMS Central Tracker

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  1. A Rad-Hard Slow Control Networkfor the CMS Central Tracker A. Marchioro, G. Cervelli, F. Faccio, K. Kloukinas, C. Ljuslin, P. Moreira, E. Murer, C. Paillard, F. VaseyCERN-EP

  2. Outline • Motivations and Requirements • Architecture • Network and system components: • Token-Ring Network • Local Monitoring • Timing and Trigger Distribution • Network: High level protocol • Project Status A. Marchioro / EP

  3. Motivations • Requirements and Architecture no different from traditional slow control system • Merging with timing distribution: unusual ! • Commercial rad-hard control components exist, but not suitable for application and expensive • Special concern: reliability and SEU robustness • Looked at commercial networks: • Ethernet • Mil1553 • CANbus • IBM Token-ring • JTAG • Other Field-buses … Either too complicated, or don’t work in magnetic fields or unsuitable or too expensive, or… A. Marchioro / EP

  4. Requirements • Must carry data and 40 MHz clock for system synchronization • Bi-directional • 150m optical + ~10 m copper • Compatible with opto-electronics used for data read-out • Redundancy • Low digital noise • Easy interfaces on the FE ASICs • ~120,000 FE ASICs, ~20,000 MCMs, ~2,000 controllers, ~200 links, ~50 control boards in Countingroom • Low cost (node price < 100 $ ) A. Marchioro / EP

  5. Outline • Motivations and Requirements • Architecture • Network and system components: • Token-Ring Network • Local Monitoring • Timing and Trigger Distribution • Network: High level protocol • Project Status A. Marchioro / EP

  6. CMS Tracker R-O: General Architecture APVs to DAQ Det A/D Memory I V A/D DCU PLL-Delay Temp FED TTCrx Front-end Module Data Path I2C CLK & T1 Control Path CLK - T1 TTCrx CCU CCU FEC cntrl PCI Intfc CCU CCU FEC Control Module A. Marchioro / EP

  7. ChannelController ChannelController ChannelController ChannelController Logical View of Control Ring Simple JTAG, i.e. JTAG sequences setup in SW in FEC Channel Specific Protocols I2C MBUS PIO JTAG FEC I2C - MBUS etc. Channels PCI OA O/E NodeController Node Node CCU_8 CCU_1 Ring Protocol A. Marchioro / EP

  8. Full control ring Wires between CCU and FE modules CLK+T1 1 * diff pair (LVDS) I2C 2 (TTL OC) Alarm 1 (TTL OC) Wires between CCU modules CLK+T1 1 diff pair (LVDS) Data 1 diff pair (LVDS) Reset 1 wire (TTL) ( x 2 for redundancy) FE APV module APVs- PLL Mux-Laser driver CCU module CCU LVDS driver O/E converter Dig. laser driver Dig receiver LVDS driver A. Marchioro / EP

  9. “Module Skip” Redundancy DOut Secondary CCU CCU CCU CCU DIn + Clk Primary DCU DCU DCU DCU CCU A. Marchioro / EP

  10. Outline • Motivations and Requirements • Architecture • Network and system components: • Token-Ring Network • Local Monitoring • Timing and Trigger Distribution • Network: High level • Project Status A. Marchioro / EP

  11. FEC: Front-End Control Board PCI/PMC Connector PCI Adapter FIFOs XTAL Control Logic TTCrx LVDS Optical Intfc. From TTC net 4-way ribbon (8 with redundancy) A. Marchioro / EP

  12. CCU: Communication and Control Unit Power Control Ext Reset* Trigger Decoder L1 CLKI(A) ST1 Clock Distribution ST2 CLKI(B) ST3 ST4 CLKO(A) Tj Counter & other timing logic Protocol Adapter & Address Decoder DO(A) Link Controller DI(A) CLKO(B) DO(B) I2C Master Intfc. SCL SDA DI(B) Memory Bus Interface PIO 18 x I2C Buses I2C Master Intfc. D[0:7] A[0:7] R/W CS* PDA[0:7] PDB[0:7] Local Bus A. Marchioro / EP

  13. CCU-M Cabling With Redundancy CCU Data In-Port A Data Out-Port A Data In-Port B Data Out-Port B Clk In-Port A Clk In-Port B PLLCKSEL CKOSEL DIn_A DOut_A DIn_B DOut_B ClkIn_A ClkOut_A ClkIn_B ClkOut_B PLL_Clk A. Marchioro / EP

  14. Coding of Clock and T1: Two Options ~ 25 ns Used CLK T1 CLK+T1 ( ) 25 ns CLK T1 ~ 8 ns ~ 16 ns CLK+T1 A. Marchioro / EP

  15. NRZ_I (Invert 1 on Change) Coding • “0” : no transitions ( < 3 conseq.) • “1” : transition at start of cycle 25 ns 1 1 1 1 0 0 0 1 0 1 A. Marchioro / EP

  16. Hard Reset (i.e. how to get always out of troubles) Din Reset Din Reset Vref • Power-Up reset only must be avoided • use long sequence of 1’s (invalid data sequence) in data stream • extra comparator in receiver ASIC A. Marchioro / EP

  17. 4-5 Bit Encoding NRZI decoder 4 to 5 bit 5 to 4 bit NRZI encoder A. Marchioro / EP

  18. reset Reset block B.F. PIN diode in LVDS Tx preamplifier L.A. L.A. L.A. L.A. out sf Other network components • RX40: a RH 80 MHz BW digital receiver with Automatic Gain Control • Laser Driver: a RH Linear driver for analog and digital data RX40 Exists already A. Marchioro / EP

  19. DCU: Detector Control Unit • Local Monitoring • Current Sensing • Voltage Monitor • Temperatures Bias Generator for Modulator 12 bit A/D 8 Inputs Input Mux SCL SDA Bus Interface Control STM Temp Sensor Control / Status & Data Registers • Designed in ¼ mm CMOS • ~ 2x2 mm2 • I2C Interface • < 10 mW • 100 msec/conversion A. Marchioro / EP

  20. Timing Distribution: PLL-Delay CLK Delay Lines CLK & T1 extract CLK&T1 PLL T1 I2C Slave Interface I2C_Add (hardwired) SDA SCL A. Marchioro / EP

  21. Library for digital designs Well isolation NMOS enclosed NMOS guard-ring A. Marchioro / EP

  22. Digital Library Features Envisaged Operating Voltage 1001 Elements Ring Oscillator in 0.25 mm Power: 0.05 mW/gate*MHz @ 1 V 0.25 mW/gate*MHz @ 2.5 V A. Marchioro / EP

  23. Outline • Motivations and Requirements • Architecture • Network and system components: • Token-Ring Network • Local Monitoring • Timing and Trigger Distribution • Network: High level protocol • Project Status A. Marchioro / EP

  24. LAN Protocol • Inspired by Token-Ring • Can work with single master and “simpler” slaves • Extensible to any local protocol (I2C. Memory, etc.) • Max data rate: 32 Mbit/sec A. Marchioro / EP

  25. LAN Protocol (1) • Ring-like topology • Circulating token indicates bus available • Source node waits for token: • Removes token, inserts data packet • Packet circulates, passed by all nodes • Destination copies packet, sets “S” symbol • Packet returns to source, is removed by source • Source node inserts new token A. Marchioro / EP

  26. LAN Protocol (2) • All nodes can generate packets • For simplicity: • Only the FEC can perform network supervision • Inserts first token • Monitors token integrity • Receives all data packets from CCUs • FEC requires CPU for protocol management A. Marchioro / EP

  27. LAN Protocol: Packet Format Universal SOF Dest Src Length Data CRC EOF Channel Specific Ch# Cmd TR# Addr DW (Example for an I2C byte write) A. Marchioro / EP

  28. LAN Protocol (3a): Write Example • Transaction sequence: • FEC sends command packet • CCU receives packet and sets “S” symbol • Command packet returns to FEC • CCU directs data portion to channel • Channel performs action • Channel sends ACK packet to CCU specifying TR# A. Marchioro / EP

  29. LAN Protocol (3b): Read Example • Transaction sequence: • FEC sends command packet • CCU receives packet and sets “S” symbol • Command packet returns to FEC • CCU directs data portion to channel • Channel performs read action • Channel sends data back to CCU specifying TR# A. Marchioro / EP

  30. LAN Protocol (4): Addressing • CCU Address allocation • FEC has address 0x00 • Special Broadcast class: 0xf_ • Up to 254 CCUs on ring • Channel Addressing • 0: CCU Node controller • 1-15: I2C channels • 16-31: memory channels • 32-47: PIO channel (e.g. HV switches) • 48-63: Event memory controller A. Marchioro / EP

  31. Software Architecture • Lynx-OS • WinNT • Linux ? • Features: • Multi-User • Multi-Task • Synchronous (wait for Ack.) User Application 1 User Application N Sync I/O Driver Interrupt Handler Packet Driver PCI-Hardware A. Marchioro / EP

  32. Outline • Motivations and Requirements • Architecture • Network and system components: • Token-Ring Network • Local Monitoring • Timing and Trigger Distribution • Network: High level protocol • Project Status A. Marchioro / EP

  33. Project Status: Hardware • FEC: PCI-PMC version exists using FPGAs • CCU: rad-soft, 6 I2C channels, 0.6 mm CMOS version is fully functional • Currently being remapped to ¼ mm technology, submission ~ Q1 ‘01 • Full ASIC > 250,000 gates • PLL: exists and is OK in ¼ mm CMOS • DCU: design ready for submission Q1 ‘00  • RX40: exists in ¼ mm, design OK • Laser Driver: rad soft OK, RH submission Q1 ‘00  • Cost: components well within requirements A. Marchioro / EP

  34. Project Status: Software • You always end up needing more software than you expected • Low level routines: OK • Partitioning architecture: work started • Performance under WinNT: • 200,000 I2C transactions/sec (limited by I2C, polling) A. Marchioro / EP

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