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Semiconductor Memories

Semiconductor Memories

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Semiconductor Memories

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  1. Semiconductor Memories Lecture 1: May 10, 2006 EE Summer Camp Abhinav Agarwal

  2. Outline • Concept/need of memory • Parameters • Types/classification • Basic features • Basic Cell circuits • Peripheral circuitry

  3. Concept • Data storage essential for processing • Binary storage • Switches • How do you implement this in Hardware?

  4. Requirements • Easy reading • Easy Writing • High density • Speed, more speed and still more speed

  5. Memory Chip Configuration

  6. Semiconductor Memory Classification Non-Volatile Read-WriteMemory Read-Write Memory Read-Only Memory Random Non-Random EPROM Mask-Programmed Access Access 2 E PROM Programmable (PROM) FLASH FIFO SRAM LIFO DRAM Shift Register CAM

  7. RAM • Random write and read operation for any cell • Volatile data • Most of computer memory • DRAM • Low Cost • High Density • Medium Speed • SRAM • High Speed • Ease of use • Medium Cost

  8. ROM • Non-volatile Data • Method of Data Writing • Mask ROM • Data written during chip fabrication • PROM • Fuse ROM: Non-rewritable • EPROM: Erase data by UV rays • EEPROM: Erase and write through electrical means • Speed 2-3 times slower than RAM • Upper limit on write operations • Flash Memory – High density, Low Cost

  9. Basic Cells SRAM • DRAM

  10. Bit Bit Bit Bit Bit Bit Word M8 M9 M4 M5 CAM ••• CAM M6 M7 Word S S Word int CAM ••• CAM M3 M2 Match M1 Wired-NOR Match Line Static CAM Memory Cell ••• •••

  11. CAM in Cache Memory CAM SRAM ARRAY ARRAY Hit Logic Address Decoder Input Drivers Sense Amps / Input Drivers Address Tag Hit R/W Data

  12. ROM EEPROM • Fuse ROM Floating Gate

  13. MOS NAND ROM V DD Pull-up devices BL [0] BL [1] BL [2] BL [3] WL [0] WL [1] WL [2] WL [3] All word lines high by default with exception of selected row

  14. D G S Non-Volatile MemoriesThe Floating-gate transistor (FAMOS) Floating gate Gate Source Drain t ox t ox + +_ n n p Substrate Schematic symbol Device cross-section

  15. 20 V 0 V 5 V 20 V 0 V 5 V 10 V 5 V 5 V 2.5 V - - S D S D S D Avalanche injection Removing programming voltage leaves charge trapped Programming results in higher V . T Floating-Gate Transistor Programming

  16. A “Programmable-Threshold” Transistor

  17. Periphery • Decoders • Sense Amplifiers • Input/Output Buffers • Control / Timing Circuitry

  18. Row Decoders Collection of 2M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder

  19. Hierarchical Decoders Multi-stage implementation improves performance • • • WL 1 WL 0 A A A A A A A A A A A A A A A A 0 1 0 1 0 1 0 1 2 3 2 3 2 3 2 3 • • • NAND decoder using 2-input pre-decoders A A A A A A A A 1 0 0 1 3 2 2 3

  20. D make V as small × D C V as possible t = ---------------- p I av large small Sense Amplifiers Idea: Use Sense Amplifer small s.a. transition input output

  21. V V (1) BL V PRE D V (1) V (0) t Sense amp activated Word line activated Sense Amp Operation

  22. Differential Sense Amplifier V DD M M 3 4 y Out M M bit bit 1 2 M SE 5 Directly applicable toSRAMs

  23. Reliability and Yield

  24. References • Digital Integrated Circuits, 2nd Edition, Jan Rabaey, Anantha Chandrakasan, Borivoje Nikolic Chapter 12 http://bwrc.eecs.berkeley.edu/IcBook/slides.htm • Sedra & Smith, Microelectronic Circuits, 4th Edition, Chapter 13 • Section 13.9, 13.10, 13.11, 13.12 • VLSI Memory Chip Design, Kiyoo Itoh