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Semiconductor Memories

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  1. Digital Integrated Circuit Design Andrea Bonfanti DEIB Via Golgi 40, Milano Semiconductor Memories

  2. Chapter Overview • Memory Classification • Memory Architectures • The Memory Core • Periphery • Reliability

  3. Semiconductor Memory Classification Non-Volatile Read-WriteMemory Read-Write Memory Read-Only Memory Random Non-Random EPROM Mask-Programmed PROM Access Access 2 E PROM FLASH FIFO SRAM LIFO DRAM Shift Register CAM

  4. Memory Timing: Definitions

  5. Decoder reduces the number of select signals K = log N 2 Memory Architecture: Decoders M bits M bits S S 0 0 Word 0 Word 0 S 1 Word 1 Word 1 A 0 S Storage Storage 2 Word 2 Word 2 A cell cell 1 N words Decoder A K-1 S N-2 Word N-2 Word N-2 S N-1 Word N-1 Word N-1 Input-Output Input-Output ( M bits) ( M bits) Intuitive architecture for N x M memory Too many select signals: N words == N select signals

  6. Array-Structured Memory Architecture Problem: ASPECT RATIO or HEIGHT >> WIDTH + - Amplify swing to rail-to-rail amplitude Selects appropriate - word

  7. Hierarchical Memory Architecture Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings

  8. Read-Only Memory Cells BL BL VDD WL WL BL BL WL WL GND MOS ROM 1 MOS ROM 2

  9. MOS OR ROM BL [0] BL [1] BL [2] BL [3] WL [0] V DD WL [1] WL [2] V DD WL [3] V bias Pull-down loads

  10. MOS NOR ROM V DD Pull-up devices WL [0] GND WL [1] WL [2] GND WL [3] BL [0] BL [1] BL [2] BL [3]

  11. MOS NOR ROM Layout Cell (9.5l x 7l) WL0 Programming using the Active Layer Only GND WL1 WL2 Polysilicon GND Metal1 Diffusion WL3 Metal1 on Diffusion BL3 BL2 BL1 BL0

  12. MOS NOR ROM Layout Cell (11l x 7l) WL0 Programming using the Contact Layer Only GND WL1 WL2 Polysilicon Metal1 GND Diffusion WL3 Metal1 on Diffusion BL3 BL2 BL1 BL0

  13. MOS NAND ROM V DD Pull-up devices BL [0] BL [1] BL [2] BL [3] WL [0] WL [1] WL [2] WL [3] All word lines high by default with exception of selected WL

  14. No contact to VDD or GND necessary; drastically reduced cell size Loss in performance compared to NOR ROM MOS NAND ROM Layout Cell (8l x 7l) Programming using the Metal-1 Layer Only WL0 WL1 WL2 Polysilicon WL3 Diffusion Metal1 on Diffusion BL3 BL1 BL2 BL0

  15. NAND ROM Layout Cell (5l x 6l) Programming using Implants Only WL0 WL1 WL2 WL3 Polysilicon Threshold-alteringimplant BL3 BL1 BL2 BL0 Metal1 on Diffusion

  16. V DD BL r word WL C bit c word Equivalent Transient Model for MOS NOR ROM Model for NOR ROM • Word line parasitics • Wire capacitance and gate capacitance • Wire resistance (polysilicon) • Bit line parasitics • Resistance not dominant (metal) • Drain and Gate-Drain capacitance

  17. Equivalent Transient Model for MOS NAND ROM V DD Model for NAND ROM BL C L r bit c bit r word WL c word • Word line parasitics • Similar to NOR ROM • Bit line parasitics • Resistance of cascaded transistors dominates • Drain/Source and complete gate capacitance

  18. Decreasing Word Line Delay

  19. Precharged MOS NOR ROM V f DD pre Precharge devices WL [0] GND WL [1] WL [2] GND WL [3] BL [0] BL [1] BL [2] BL [3] PMOS precharge device can be made as large as necessary, but clock driver becomes harder to design.

  20. D G S Non-Volatile MemoriesThe Floating-gate transistor (FAMOS) Floating gate Control Gate Source Drain t ox t ox + +_ n n p Substrate Schematic symbol Device cross-section

  21. 20 V 0 V 5 V 20 V 0 V 5 V 10 V 5 V S D S D S D Avalanche injection Removing programming voltage leaves charge trapped Programming results in higher V . T Floating-Gate Transistor Programming

  22. A “Programmable-Threshold” Transistor

  23. FLOTOX EEPROM Gate Floating gate I Drain Source V 20 – 30 nm -10 V GD 10 V 1 1 n n Substrate p 10 nm Fowler-Nordheim I-V characteristic FLOTOX transistor

  24. V DD EEPROM Cell BL WL Absolute threshold control is hard Unprogrammed transistor might be depletion  2 transistor cell

  25. Flash EEPROM Control gate Floating gate erasure Thin tunneling oxide 1 1 n source n drain programming p- substrate Many other options …

  26. Cross-sections of NVM cells Flash EPROM Courtesy Intel

  27. Basic Operations in a NOR Flash Memory―Erase

  28. Basic Operations in a NOR Flash Memory―Write

  29. Basic Operations in a NOR Flash Memory―Read

  30. NAND Flash Memory Word line(poly) Unit Cell Source line (Diff. Layer) Courtesy Toshiba

  31. Select transistor Word lines Active area STI Bit line contact Source line contact NAND Flash Memory Courtesy Toshiba

  32. Characteristics of State-of-the-art NVM

  33. Characteristics of State-of-the-art NVM

  34. Read-Write Memories (RAM) • STATIC (SRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential • DYNAMIC (DRAM) Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended

  35. Q 6-transistor CMOS SRAM Cell WL V DD M M 2 4 Q M M 6 5 M M 1 3 BL BL

  36. CMOS SRAM Analysis (Read) WL V DD M BL 4 BL Q 0 = M Q 1 = 6 M 5 V V V M DD DD DD 1 C C bit bit

  37. CMOS SRAM Analysis (Read) 1.2 1 0.8 0.6 Voltage Rise (V) 0.4 0.2 0 0 0.5 1 1.2 1.5 2 2.5 3 Cell Ratio (CR)

  38. WL V DD M 4 M Q 0 = 6 M 5 Q 1 = M 1 V DD BL 1 BL 0 = = CMOS SRAM Analysis (Write)

  39. CMOS SRAM Analysis (Write)

  40. VDD M2 M4 Q Q M1 M3 GND M5 M6 WL BL BL 6T-SRAM — Layout

  41. Static power dissipation -- Want R large L Bit lines precharged to V to address t problem DD p Resistance-load SRAM Cell WL V DD R R L L Q Q M M 3 4 BL BL M M 1 2

  42. SRAM Characteristics

  43. BL 1 BL 2 WWL WWL RWL RWL M 3 V V X M X 2 DD T 1 M 2 V DD BL 1 C S V D BL 2 V V 2 DD T No constraints on device ratios Reads are non-destructive Value stored at node X when writing a “1” = V -V WWL Tn 3-Transistor DRAM Cell

  44. BL2 BL1 GND RWL M3 M2 WWL M1 3T-DRAM — Layout

  45. C S ------------ V V D = – V = V – V BL PRE BIT PRE C + C S BL 1-Transistor DRAM Cell - Write: C is charged or discharged by asserting WL and BL. S Read: Charge redistribution takes places between bit line and storage capacitance Voltage swing is small; typically around 250 mV.

  46. DRAM Cell Observations • 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. • DRAM memory cells are single ended in contrast to SRAM cells. • The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. • Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. • When writing a “1” into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value thanVDD.

  47. V V (1) BL V PRE D V (1) V (0) t Sense amp activated Word line activated Sense Amp Operation

  48. Metal word line SiO 2 Poly Field Oxide Diffused + + n n bit line Inversion layer Poly Polysilicon induced by Polysilicon plate plate bias gate 1-T DRAM Cell Capacitor M word 1 line Cross-section Layout Uses Polysilicon-Diffusion Capacitance Expensive in Area

  49. SEM of poly-diffusion capacitor 1T-DRAM

  50. Advanced 1T DRAM Cells Word line Capacitor dielectric layer Cell plate Insulating Layer Cell Plate Si Transfer gate Isolation Refilling Poly Capacitor Insulator Storage electrode Storage Node Poly Si Substrate 2nd Field Oxide Stacked-capacitor Cell Trench Cell