Digital Integrated Circuits Prentice Hall 1995. Memory. Array-Structured Memory ... transistor (FAMOS) Digital Integrated Circuits Prentice Hall 1995 ...
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Capacitor dielectric layer
Cell Plate Si
Storage Node Poly
2nd Field Oxide
Collection of 2M complex logic gates
Organized in regular and dense fashion
Yield curves at different stages of process maturity
Memory Size as a function of time: x 4 every three years
Increasing die size
factor 1.5 per generation
Combined with reducing cell size
factor 2.6 per generation
Technology feature size for different SRAM generations