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VLSI Design Using PC-Based Tools. Cherrice Traver Union College Schenectady, NY. Why use PC-based tools?. Outline. Tanner Research Tools for Education Practical issues Tool flow and capabilities Example use Curriculum examples. Practical Issues System Requirements.

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vlsi design using pc based tools

VLSI Design Using PC-Based Tools

Cherrice Traver

Union College

Schenectady, NY

PC-Based VLSI Design Tools

Cherrice Traver

why use pc based tools

Why use PC-based tools?

PC-Based VLSI Design Tools

Cherrice Traver

outline
Outline

Tanner Research Tools for Education

  • Practical issues
  • Tool flow and capabilities
  • Example use
  • Curriculum examples

PC-Based VLSI Design Tools

Cherrice Traver

practical issues system requirements
Practical IssuesSystem Requirements

Minimumrequirements

  • 100 MHz PCs, 32M RAM

Recommended

  • 500 MHz PCs, 256M RAM
  • 3-button mouse

PC-Based VLSI Design Tools

Cherrice Traver

practical issues installation
Practical IssuesInstallation
  • Tool installation - Install-Shield Wizard
  • License server
    • Sentinel LM on NT Server
    • Floating individual tool licenses

PC-Based VLSI Design Tools

Cherrice Traver

practical issues tool choices
Practical IssuesTool Choices

L-Edit

DRC EXT SPR

L-Edit Pro

CMOS Libraries

Tspice S-Edit W-Edit

T-Spice Pro

Design Pro

Tanner Tools Pro

PC-Based VLSI Design Tools

Cherrice Traver

practical issues cost and maintenance
Practical IssuesCost and Maintenance
  • Educational pricing
  • Quantity pricing
  • Free support for 60 days
  • No annual maintenance fee required
  • 15% maintenance fee per year for updates and continued support

PC-Based VLSI Design Tools

Cherrice Traver

practical issues documentation
Practical IssuesDocumentation

Help Menu Indexed PDF Manual

PC-Based VLSI Design Tools

Cherrice Traver

contact information
Contact Information

Janice Barthelemy

Account Manager

janice@tanner.com

Tanner EDA

2650 East Foothill Blvd.

Pasadena, CA 91107

Toll free (877) 325-2223

Fax (626) 792-0300

www.tanner.com

PC-Based VLSI Design Tools

Cherrice Traver

simplified tanner tool flow
Simplified Tanner Tool Flow

S-Edit TM

Schematic Editor

T-Spice TM

Circuit Simulator

W-Edit TM

Waveform Viewer

L-Edit TM

Full Custom Layout Editor

GDS II & CIF

PC-Based VLSI Design Tools

Cherrice Traver

overview of examples
Overview of Examples
  • Layout Editor - L-Edit
  • Schematic Editor - S-Edit
  • Standard Cell Place and Route - SPR
  • Spice simulator - T-Spice

PC-Based VLSI Design Tools

Cherrice Traver

l edit tool flow
L-Edit: Tool Flow

S-Edit TM

T-Spice TM

Layout Libraries

SCMOSLib

...

L-Edit/SPR TM

Standard Cell

Place & Route

L-Edit/Extract TM

General Device

Extractor

L-Edit TM

Full Custom Layout Editor

L-Edit/DRC TM

On-line Design

Rule Checker

Cross Section

Viewer

PC-Based VLSI Design Tools

Cherrice Traver

l edit layout editor features
L-Edit: Layout Editor Features

PC-Based VLSI Design Tools

Cherrice Traver

l edit example
L-Edit: Example

CMOS Inverter

  • Layout Editing
  • DRC
  • Cross Section Viewing
  • Extract Spice File

PC-Based VLSI Design Tools

Cherrice Traver

s edit tool flow
S-Edit: Tool Flow

Technology Mapping

Library

SCMOS

...

SchemLib TM

Technology

Independent

Library

S-Edit TM

Schematic Editor

netlist

extract

NetTran

T-Spice TM

SPR

L-Edit TM

PC-Based VLSI Design Tools

Cherrice Traver

s edit schematic editor features
S-Edit: Schematic Editor Features

PC-Based VLSI Design Tools

Cherrice Traver

s edit example
S-Edit: Example

Full Adder Circuit

  • Schematic Drawing
  • Spice Export
  • Tanner Place and Route Export

PC-Based VLSI Design Tools

Cherrice Traver

spr tool flow
SPR: Tool Flow

S-Edit TM

.tpr file

Layout Libraries

SCMOSLib

...

L-Edit/SPR TM

Standard Cell

Place & Route

L-Edit TM

Full Custom Layout Editor

PC-Based VLSI Design Tools

Cherrice Traver

spr example
SPR: Example

Full Adder Circuit

  • L-Edit - Place and Route
  • Core + Padframe
  • Extract Spice Circuit

PC-Based VLSI Design Tools

Cherrice Traver

t spice and w edit tool flow
T-Spice and W-edit: Tool Flow

S-Edit TM

netlist extract

T-Spice TM

Circuit Simulator

W-Edit TM

Waveform Viewer

device extract

L-Edit TM

PC-Based VLSI Design Tools

Cherrice Traver

t spice and w edit features
T-Spice and W-edit: Features
  • Menu-based command insertion
  • Integrated W-Edit waveform viewer
  • Circuit Probing from S-Edit

PC-Based VLSI Design Tools

Cherrice Traver

t spice and w edit example
T-Spice and W-edit: Example

Full Adder simulation

  • Simulation of schematic netlist
  • Waveform probing
  • Simulation of extracted layout

PC-Based VLSI Design Tools

Cherrice Traver

tool integration in vlsi design course
Tool Integration in VLSI Design Course

Laboratories

  • Tool use
  • Reinforcement of lecture topics

Project

  • Behavior --> Layout design experience

PC-Based VLSI Design Tools

Cherrice Traver

laboratories
Laboratories

Lab 1 - L-Edit/T-Spice

  • Extract/simulate NAND gate
  • Layout/extract/simulate inverter

Lab 2 - L-Edit/T-Spice

  • Manual placement/routing standard cells
  • Manual stick diagrams
  • Extraction/simulation

Lab 3 - S-Edit/L-Edit/SPR/T-Spice

  • Schematic capture - netlist simulation
  • Standard cell place/route

PC-Based VLSI Design Tools

Cherrice Traver

kitchen timer project from modern vlsi design systems on silicon wayne wolf
Kitchen Timer Projectfrom Modern VLSI Design: Systems on Silicon, Wayne Wolf

PC-Based VLSI Design Tools

Cherrice Traver

buzz circuit
Buzz Circuit

Schematic Given - Lab Exercise

PC-Based VLSI Design Tools

Cherrice Traver

display circuit
Display Circuit

Block Diagram Given - Lab Exercise

PC-Based VLSI Design Tools

Cherrice Traver

controller
Controller
  • Specified by state diagram and VHDL model
  • Logic simulation outputs provided

PC-Based VLSI Design Tools

Cherrice Traver

timer
Timer

PC-Based VLSI Design Tools

Cherrice Traver

support provided
Support Provided
  • VHDL “Golden” behavioral model
  • Simulation output results
  • Lots of guidance on debugging

PC-Based VLSI Design Tools

Cherrice Traver

top level schematic
Top Level Schematic

PC-Based VLSI Design Tools

Cherrice Traver

kitchen timer chip statistics
Kitchen Timer Chip Statistics
  • 600 Gates
  • 8000 Transistors
  • Layout area: 1550 um x 1375 um

PC-Based VLSI Design Tools

Cherrice Traver

final layout
Final Layout

PC-Based VLSI Design Tools

Cherrice Traver

mosis fabrication
MOSIS Fabrication
  • Pads provided
  • Flatten layout
  • Export CIF file

PC-Based VLSI Design Tools

Cherrice Traver

other past designs using tanner tools
Other Past DesignsUsing Tanner Tools
  • Quadrature Decoder

http://doc.union.edu/154/Quad.decode.project/index.html

  • Simple Floating-Point Multiplier

http://doc.union.edu/154/Mult.project/mult.project.html

PC-Based VLSI Design Tools

Cherrice Traver

conclusion
Conclusion
  • Ease of Installation/Maintenance
  • Reasonable Design Flow
  • Good Interface for MOSIS Fabrication

PC-Based VLSI Design Tools

Cherrice Traver

ad