VLSI System Design

1. VLSI System Design Lecture 1.3 Hardware Description Languages (HDLs) Engr. Anees ul Husnain ( anees.buzdar@gmail.com ) Department of Computer Systems Engineering, College of Engineering & Technology, IUB

2. In this Lecture • Design steps • Designing through HDLs • Introduction HDLs • What and why HDL • Verilog HDL • Modelling a simple circuit. • Delays • Stimulus

3. Design Steps in an IC • DESIGNING CHIPS THROUGH HDLs • Advance Digital Design/ Digital Electronics • + • VLSI System Design

4. Design Steps in an IC • Design Description • Optimization • Simulation • Synthesis + • Physical design • Critical sub-systems • Enhancing speeds through design • Floor planning n so on…

5. Design Steps in an IC An industrial level overview

6. Hardware Description Language (HDL) • Basic idea is a programming language to describe hardware • Initial purpose was to allow abstract design and simulation • Design could be verified then implemented in hardware • Now Synthesis tools allow direct implementation from HDL code. • Large improvement in designer productivity

7. HDL • HDL allows write-run-debug cycle for hardware development. • Similar to programming software • Much, much faster than design-implement-debug • Combined with modern Field Programmable Gate Array chips large complex circuits (100000s of gates) can be implemented.

8. HDLs • There are many different HDLs • Verilog HDL • ABEL – Advance Boolean Expressions Language • VHDL • VHDL is the most common • Large standard developed by US DoD • VHDL = VHSIC HDL • VHSIC = Very High Speed Integrated Circuit

9. Verilog HDL • Verilog HDL is second most common • Easier to use in many ways = better for teaching • C - like syntax • History • Developed as proprietry language in 1985 • Opened as public domain spec in 1990 • Due to losing market share to VHDL • Became IEEE standard in 1995

10. Verilog HDL • Verilog constructs are use defined keywords • Examples: and, or, wire, input output • One important construct is the module • Modules have inputs and outputs • Modules can be built up of Verilog primatives or of user defined submodules.

11. Example: Simple Circuit Diagram

12. Example: Simple Circuit HDL module smpl_circuit(A,B,C,x,y); input A,B,C; output x,y; wire e; and g1(e,A,B); not g2(y, C); or g3(x,e,y); endmodule

13. Simple Circuit Notes • The module starts with module keyword and finishes with endmodule. • Internal signals are named with wire. • Comments follow // • inputand output are ports. These are placed at the start of the module definition. • Each statement ends with a semicolon, except endmodule.

14. Circuit to code module smpl_circuit(A,B,C,x,y); input A,B,C; output x,y; wire e; and g1(e,A,B); not g2(y, C); or g3(x,e,y); endmodule

15. Adding Delays • To simulate a circuits real world behaviour it is important that propagation delays are included. • The units of time for the simulation can be specified with timescale. • Default is 1ns with precision of 100ps • Component delays are specified as #(delay)

16. Simple Circuit with Delay module circuit_with_delay (A,B,C,x,y); input A,B,C; output x,y; wire e; and #(30) g1(e,A,B); or #(20) g3(x,e,y); not #(10) g2(y,C); endmodule

17. Effect of delay

18. Input signals • In order to simulate a circuit the input signals need to be known so as to generate an output signal. • The input signals are often called the circuit stimulus. • An HDL module is written to provide the circuit stimulus. This is known as a testbench.

19. Testbench • The testbench module includes the module to be tested. • There are no input or output ports for the testbench. • The inputs to the test circuit are defined with reg and the outputs with wire. • The input values are specified with the keyword initial • A sequence of values can be specified between begin and end.

20. Signal Notation • In Verilog signals are generalised to support multi-bit values (e.g. for buses) • The notation A = 1’b0; • means signal A is one bit with value zero. • The end of the simulation is specified with $finish.

21. Stimulus module for simple circuit module stimcrct; reg A,B,C; wire x,y; circuit_with_delay cwd(A,B,C,x,y); initial begin A = 1'b0; B = 1'b0; C = 1'b0; #100 A = 1'b1; B = 1'b1; C = 1'b1; #100 $finish; end endmodule

22. Tools you’re equipped with… • Xilinx ISE • ISE Simulator

23. Language what you need • Verilog… • Syntax & Structure (at Lab hours)