EE4271 VLSI Design

1. EE4271 VLSI Design Dr. Shiyan Hu Office: EERC 731 shiyan@mtu.edu The Inverter Adapted and modified from Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic.

2. Circuit Symbols

3. V DD S D V V in out D C L S The CMOS Inverter: A First Glance Vin=Vdd,Vout=0 Vin=0,Vout=Vdd

4. V V DD DD R p V out V out R n V V V 0 in DD in CMOS Inverter - First-Order DC Analysis

5. CMOS Inverter: Transient Response V V DD DD Delay=0.69RC R p V out V out C L C L R n V 0 V V in DD in (a) Low-to-high (b) High-to-low

6. NMOS In Inverter V DD S D V V in out D C L S • For NMOS • Vin=0, Vgsn=0<Vtn, Vdsn=Vout=Vdd, NMOS is in cut-off region, X1. • PMOS is on. Vout=Vdd. • Vin=Vdd, instantaneously, Vgsn=Vdd>Vtn,Vdsn=Vout=Vdd, Vgsn-Vtn=Vdd-Vtn<Vdd, NMOS is in saturation region, X2 • Instantaneously, Vgsp=0>Vtp. PMOS cut-off • NMOS is on so Vdsn->0. The operating point follows the arrow to the origin. Vout=0 at X3.

7. V DD S D V V in out D C L S The CMOS Inverter We enforce that Idsp=-Idsn when both transistors are on for DC analysis. Assume that Vtn=|Vtp|

8. V DD V V in out C L The CMOS Inverter – 2 (Region A) 0<Vin<Vtn |Vgsp|=|Vin-Vdd|>|Vtp|, |Vdsp|=|Vd-Vdd|~0<|Vgsp-Vtp| PMOS linear region S D Vd is close to Vdd D S Vgsn=Vin<Vtn, NMOS cut-off

9. V DD V V in out C L The CMOS Inverter – 3(Region B) Vtn<Vin<Vdd/2 |Vgsp|=|Vin-Vdd|>Vdd/2>|Vtp|, |Vdsp|~0<|Vgsp-Vtp| PMOS linear region S D D S Vgsn=Vin>Vtn, Vdsn=Vout=Vdd>Vgsn-Vtn NMOS saturation region

10. The CMOS Inverter - 4

11. V DD V V in out C L The CMOS Inverter – 5(Region C) Vin=Vout |Vgsp|=|Vin-Vdd|>|Vtp|, |Vdsp|>|Vgsp-Vtp|, saturation Vgsn=Vdsn Vgsp=Vdsp S D D S Vgsn>Vtn, Vdsn>Vgsn-Vtn, saturation

12. The CMOS Inverter - 6 Usually, Usually we set for equal rising and falling propagation delay (same R for both devices) Since , we have

13. The CMOS Inverter 7 • Vin=Vout=Vdd/2 • The above analysis is actually correct for Vin=vdd/2 and all Vout such that both devices are in saturation regions • For NMOS, Vout>Vin-Vtn • For PMOS, Vgsp-Vtp>Vdsp ->Vout<Vin-Vtp • Vin-Vtn<Vout<Vin-Vtp, so for Vin=Vdd/2, Vout can vary around Vdd/2

14. V DD V V in out C L The CMOS Inverter – 9(Region D) Vdd/2<Vin<Vdd-|Vtp| |Vgsp|=|Vin-Vdd|>|Vtp|, |Vdsp|=|Vd-Vdd|>|Vgsp-Vtp|, PMOS saturation region S D Vout < Vdd/2 D S Vgsn=Vin>Vtn, Vdsn=Vout<Vgsn-Vtn NMOS linear region

15. The CMOS Inverter - 10

16. V DD V V in out C L The CMOS Inverter – 11(Region E) Vin>Vdd-|Vtp| |Vgsp|=|Vin-Vdd|<|Vtp|, PMOS cut-off S D D S Vgsn=Vin>Vtn, Vdsn<Vgsn-Vtn NMOS linear

17. The CMOS Inverter -12

18. The CMOS Inverter

19. Circuit Under Design

20. Its Layout View