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Senior Project Presentation. S J S U. Spring 2002. A Four-bit ALU for a SOC Library. Presented by Juan González & Prashanta Lal Advisor: Dr. David W. Parent. Outline. Project Goals Motivation Project Overview Design process flow methodology of the ALU Summary Conclusion

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senior project presentation
Senior Project Presentation

S J S U

Spring 2002

a four bit alu for a soc library

A Four-bit ALU for a SOC Library

Presented by

Juan González & Prashanta Lal

Advisor: Dr. David W. Parent

outline
Outline
  • Project Goals
  • Motivation
  • Project Overview
  • Design process flow methodology of the ALU
  • Summary
  • Conclusion
  • Acknowledgments
project goal
Project Goal
  • Document the IC front-to-back CMOS design process flow for a 4 bit Arithmetic Logic Unit using 1.5m and 3.0m technology.
motivation
Motivation
  • The importance of CMOS technology in industry.
  • The challenge of processing reliable CMOS systems at SJSU’s fabrication facilities.
  • Gateway to advanced senior design projects in the area of semiconbductor devices and IC design.
  • Meeting ABET standards in time.
  • Contributing to CMOS research at San Jose State.
project overview
Project Overview
  • Investigate the front-to-back IC design methodology:
    • Design
    • Simulation
    • Verification
    • Fabrication
    • Testing

……….. Of a 4 - bit Arithmetic Logic Unit.

74hc181 features
74HC181 Features
  • Full look-ahead for high speed operation on long words.
  • Arithmetic operating modes:

-Addition, Subtraction

  • Logic function modes:

- NAND, AND, OR, NOR, EX-OR, Comparator plus ten other logic operations.

  • Wide operating voltage range: 2V-6V.
design process methodology of the alu
Design Process Methodology of the ALU
  • Sizing Transistors through the use of analytical equations.
  • CAD tool design.
  • Fabrication of the device.
  • Testing of the device.
  • Documentation of the process.
slide10

Logic Diagram Schematic

From National S.C.

F13

F1

F16

F14

F2

F15

F18

F3

F7

F17

F8

F4

F20

F9

F19

F25

F10

F5

F22

F11

F21

F12

F6

F23

F24

function minimization
Function Minimization

CommonTerms:

Substituting H and K into functions:

transistor design
Transistor Design
  • And-Or-Invert design technique.
  • Euler Path design.
  • Stick diagram technique.
cad tool design
CAD tool design
  • Cell-based circuit implementation.
  • Simulation.
  • Layout.
  • Design Rule Check.
  • Layout versus Schematic Check.
  • Extraction.
  • Post Simulation.
fabrication
Fabrication
  • SJSU IC Process Lab Room E311.
  • 7 Mask CMOS process.
  • 1.5m and 3.0m technology.
  • In correlation with the EE167 Course.
laboratory constraints
Laboratory Constraints
  • Statistical Process Control Analysis
  • Problems Encountered
testing
Testing
  • Currently underway.
  • Now testing metal contacts, nmos and pmos structures.
  • Device testing will be done using Agilent’s Logic Analyzer.
documentation
Documentation
  • Transistor Design
  • CAD simulation Analysis
  • Fabrication – CMOS process traveler
  • Testing Analysis
conclusion
Conclusion
  • Successful design, simulation and fabrication of the first major system at San Jose State’s fabrication facilities.
  • Contribution to research and development of IC integrated circuit design.
acknowledgments
Acknowledgments
  • Dr. Parent
  • Eric Basham
  • Dan Hicks
  • Neil Peters
  • EE167 Classmates