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Senior Project Presentation

Senior Project Presentation. S J S U. Spring 2002. A Four-bit ALU for a SOC Library. Presented by Juan González & Prashanta Lal Advisor: Dr. David W. Parent. Outline. Project Goals Motivation Project Overview Design process flow methodology of the ALU Summary Conclusion

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Senior Project Presentation

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  1. Senior Project Presentation S J S U Spring 2002

  2. A Four-bit ALU for a SOC Library Presented by Juan González & Prashanta Lal Advisor: Dr. David W. Parent

  3. Outline • Project Goals • Motivation • Project Overview • Design process flow methodology of the ALU • Summary • Conclusion • Acknowledgments

  4. Project Goal • Document the IC front-to-back CMOS design process flow for a 4 bit Arithmetic Logic Unit using 1.5m and 3.0m technology.

  5. Motivation • The importance of CMOS technology in industry. • The challenge of processing reliable CMOS systems at SJSU’s fabrication facilities. • Gateway to advanced senior design projects in the area of semiconbductor devices and IC design. • Meeting ABET standards in time. • Contributing to CMOS research at San Jose State.

  6. Was the project completed? Yes!

  7. Project Overview • Investigate the front-to-back IC design methodology: • Design • Simulation • Verification • Fabrication • Testing ……….. Of a 4 - bit Arithmetic Logic Unit.

  8. 74HC181 Features • Full look-ahead for high speed operation on long words. • Arithmetic operating modes: -Addition, Subtraction • Logic function modes: - NAND, AND, OR, NOR, EX-OR, Comparator plus ten other logic operations. • Wide operating voltage range: 2V-6V.

  9. Design Process Methodology of the ALU • Sizing Transistors through the use of analytical equations. • CAD tool design. • Fabrication of the device. • Testing of the device. • Documentation of the process.

  10. Logic Diagram Schematic From National S.C. F13 F1 F16 F14 F2 F15 F18 F3 F7 F17 F8 F4 F20 F9 F19 F25 F10 F5 F22 F11 F21 F12 F6 F23 F24

  11. Functions Obtained from schematic…

  12. Function Minimization CommonTerms: Substituting H and K into functions:

  13. Transistor Design • And-Or-Invert design technique. • Euler Path design. • Stick diagram technique.

  14. CAD tool design • Cell-based circuit implementation. • Simulation. • Layout. • Design Rule Check. • Layout versus Schematic Check. • Extraction. • Post Simulation.

  15. Transistor Level Design

  16. Xor Schematic

  17. Cell-Based Implementation

  18. Cell Layout

  19. Final ALU Test Bench

  20. Simulation

  21. Final ALU Layout

  22. Fabrication • SJSU IC Process Lab Room E311. • 7 Mask CMOS process. • 1.5m and 3.0m technology. • In correlation with the EE167 Course.

  23. Laboratory Constraints • Statistical Process Control Analysis • Problems Encountered

  24. Testing • Currently underway. • Now testing metal contacts, nmos and pmos structures. • Device testing will be done using Agilent’s Logic Analyzer.

  25. Documentation • Transistor Design • CAD simulation Analysis • Fabrication – CMOS process traveler • Testing Analysis

  26. Conclusion • Successful design, simulation and fabrication of the first major system at San Jose State’s fabrication facilities. • Contribution to research and development of IC integrated circuit design.

  27. Acknowledgments • Dr. Parent • Eric Basham • Dan Hicks • Neil Peters • EE167 Classmates

  28. Photo SlideShow

  29. THE END

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