Yield Estimation based on Layout & Process Data. by Karthik Subramanian Master’s Thesis Work Mar 2003. Contents. Introduction to yield. Concept of “critical area” in ICs. Interconnect yield model. Yield estimation at the schematic stage. Yield estimation at the layout stage.
Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.
Master’s Thesis Work
Cchip = Cwf/(Nchip * Y)
(a). High wafer yield through contamination control has become difficult and hard to achieve.
(b). Increase in fabless design houses, which have little control over the manufacturing process; can control costs only by optimizing designs for higher yield.
(a).Functional yield loss (Yfnc) due to spot defects (shorts & opens).
(b).Parametric yield loss (Ypar) due to global process disturbances.
Total Yield = Yfnc * Ypar
(a). The use of the metal layer is more extensive than that of any other layer in the IC.
(b). The defect count is more in the metal layer.
A = die area; D = defect density.
ACr= critical area; r0 = defect radius; r1 = half (the min. Spacing between metals); K and p are model parameters.
(a). Additional Interconnect layers.
(b). Reducing Cell Utilization.
(c).Relaxing metal design rules.
 Heineken H.T., Khare J., Maly W., “Yield loss Forecasting in the early phases of the VLSI design process”, Custom Integrated Circuits Conference, Proceedings of the IEEE, 5-8 May 1996, PP.27-30.
 Heineken H.T., Khare J., d’Abreu.M, “Manufacturability Analysis of Standard Cell libraries”, “Custom Integrated Circuits Conference”, Proceedings of the IEEE, 11-14 May 1998, PP.321-324.
 Heineken H.T., Maly W., “Manufacturability Analysis Environment – MAPEX”, Custom Integrated Circuits Conference, Proceedings of the IEEE, 1-4 May 1994, PP.309-312.
 Ouyang C.H., Pleskacz W.A., Maly W., “Extraction of critical areas for opens in large VLSI circuits”, Defect and Fault Tolerance in VLSI Systems, 1996 IEEE International Symposium on, pp.21-29.
 Heineken H.T., Maly W., “Interconnect Yield model for Manufacturability prediction in synthesis of standard cell-based designs”, Computer-Aided Design, 1996, ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on , 10-14 Nov 1996 , pp.368 –373.
 Nag P.K., Maly W., “Hierarchical extraction of critical area for shorts in very large ICs”, Defect and Fault Tolerance in VLSI Systems, 1995, Proceedings, 1995 IEEE International Workshop on, pp.19-27.
 Ouyang C., Heineken H.T., Khare J., Shaikh S., d'Abreu M., “Maximizing Wafer productivity through Layout optimizations”, VLSI Design, 2000, Thirteenth International Conference on , 2000 , pp. 192 –197.