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CMS Calorimeter Trigger. SLHC Regional Calorimeter Trigger System Design and Prototypes Tom Gorski University of Wisconsin July 20, 2009. GCT Muon Aux Card Update. RS-232. GTP Links. TTS. Pushbutton Reset (for Microblaze). S-Link Connectors. TTCrx. GCT Muon Aux Card Update.

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cms calorimeter trigger
CMS Calorimeter Trigger
  • SLHC Regional Calorimeter Trigger
  • System Design and Prototypes
  • Tom Gorski
  • University of Wisconsin
  • July 20, 2009
gct muon aux card update
GCT Muon Aux Card Update

RS-232

GTP Links

TTS

Pushbutton Reset

(for Microblaze)

S-Link Connectors

TTCrx

gct muon aux card update1
GCT Muon Aux Card Update
  • Currently developing test firmware for the Aux Card
  • Firmware to be completed in Fall, 2009
  • Test firmware is a hybrid microblaze/HDL implementation
  • User interface: C program via RS-232 to PC terminal
  • Dedicated HDL blocks to test GTP, TTC, TTS & S-Link Interfaces
slhc cal trig demonstrator
SLHC Cal. Trig. Demonstrator

SLHC Cal. Trig. Demonstrator Prototype Design

First Step: determine requirements to provide proof of principle of major elements of SLHC Cal. Trig. System

Evaluate SLHC Cal. Trig. Conceptual Design

Needs performance to incorporate algorithms

Shown by M. Bachtis, S. Dasu, K. Flood (UW) in this workshop

Compatible with firmware developed for these algos.

K. Compton, M. Schulte, et al., (UW) Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines, April 2009.

Must work with ECAL1, HCAL2 upgrade designs & eventually in combination with upgraded tracking trigger primitives

Ph. Busson1 (LLR), J. Mans2 (UMinn)

Integrated with SLHC Optical SLB

J.C. da Silva, LIP.

Clear evolutionary path from present LHC RCT

Backwards-compatible functionality maintained.

calorimeter trigger evolution
Calorimeter Trigger Evolution

Step 2: ↓ OR ↓

Step 1 (2009)

Step 3

Step 4

ETCC:TPGs

HTR:TPGs

uTCA-HTR:TPG

ETCC:TPGs

HTR:TPGs

ETCC:TPGs

uTCA-HTR:TPGs

ETCC:TPGs

uTCA-HTR:TPGs

oSLB

oSLB

SLB

SLB

SLB

oSLB

oSLB

oSLB

oSLB

RMC

RMC

RCT

RCT

RMC

oSLB

oSLB

oSLB

RCT

oSLB

RCT/

uTCA

RCT/

uTCA

Matrix& AuxCards

Cu

GCT/uTCA

GCT:Sources

GCT:Sources

GCT/uTCA

GCT:Sources

GCT/uTCA

GCT/uTCA

FO

GCT:Main

GT/GMT

GT/GMT

GT/GMT

GT/GMT

review current hcal ecal to rct link
Review: Current HCAL/ECAL to RCT Link

4X 1.2 Gbps Copper Links

(19 bits data + 5 bits Hamming per link per crossing)

RCT Receiver Card

HCAL

HTR or

ECAL

TCC

RCT

RCVR

Mezz

Vitesse

V7216 Tx

Vitesse

V7216 Rx

RCT

Phase

ASIC

4.8 Gbps aggregate

  • Intersection of 4,032 links at common destination (RCT)
  • Link Xmt & Rcv Clks are 3X the LHC Clock (~120 MHz)—no long term drift issues
  • Elastic buffers in V7216 Rx chips to manage short term clk jitter
  • RCT Phase ASIC provides channel bonding function, hamming code check, and buffering for 4X RCT processing pipeline (~160 MHz) in about 3 crossings
  • 120 MHz Link Clock skew tolerances: ±6ns @ Tx, ±1ns @ Rx
  • Scheme is stable, reliable, and has low latency
clock frequencies and data rates
Clock Frequencies and Data Rates
  • Calorimeter data produced by a 40.08 MHz synchronous process
  • Carried by high-speed serial links between processing stages
  • FPGAs support different clock domains for the high speed serial links and the programmable fabric, but at the cost of increased latency at the interface
  • Governing parameter is the Link Parallel I/O Clock Frequency
  • Key Decision: Run FPGA processing fabric and/or serial links synchronous to the LHC clock or on a decoupled timebase?
    • Decoupling frees designers to chose frequencies that maximize link data rates
    • Price of decoupling:
      • Increased latency on link/fabric interface
      • Increased complexity in pipeline control and link protocol (empty cycles)
    • Advantages of coupling:
      • Perfect match in bandwidth between calorimeter, links, and processing pipeline
      • Lowest latency on interfaces
      • Simplified pipeline control and link protocol
  • Existing Latency Constraints + Xilinx Rocket I/O Tile design exerts a strong influence towards the coupled approach
tpg decompression functions
TPG Decompression Functions
  • RCT Currently uses full LUTs for each H/E tower pair (217× 18 bits)
  • Implements arbitrary conversion function plus H/E cut for electrons
  • LUTs require significant board space, not practical for upgrade—need to go to functions instead
  • Functions can place significant demands on special FPGA resources (e.g., DSP slices, block RAM)
  • Demand depends on function type:
    • Mantissa/Exponent least costly—simple shift
    • Piecewise linear uses Add/Multiply per HCAL or ECAL tower
    • Logarithmic/Exponential about 4-8× more costly than piecewise linear
  • Will need to settle on general scheme early on in the process in collaboration with ECAL and HCAL groups
  • Pursued design approach will have parameters stored in FPGA RAM, and allow changes to them without requiring FPGA resynthesis
oslb rct side lip development
oSLB RCT side (LIP Development)
  • Latency for Current 7216-based Link:
    • 3.4 bunch crossings for cable (85ns)
    • 0.8 bunch crossings for 7216 Tx (19ns)
    • 2.5 bunch crossings for 7216 Rx (62ns)
    • TOTAL: 6.6 bunch crossings (166ns)
  • Based on what we know so far about Rocket I/O, the budget may need to be increased by 1 or 2 crossings

Repeated TPG to SLHC RCT

120.24 MHz Clock

Optical

Xmtr

FPGA

Optical

Rcvr

Incoming TPG

(4.8 Gbps from

oSLB TPG side)

120 MHz Synchronous Parallel Data to Phase ASIC

(from J. C. De Silva)

slhc rct block diagram 56 12 slice
SLHC RCT Block Diagram(56η × 12φ slice)

Output Links to GCT

TTC/DAQ Connections

Processing

Card

Processing

Card

Processing

Card

TTC/DAQ

Card

Clock and Control

Trigger

Partial-

Products

(Backplane)

Trigger

Data to

DAQ

η-sharing

Links

Input Card

Input Card

Input Card

Input Card

Input Card

Input Card

Input Card

Inter-crate

Φ-sharing Links

Inter-crate Corner-sharing

Links

HCAL/ECAL TPGs from oSLB Cards

slhc rct crate 1 of 6
SLHC RCT Crate (1 of 6)

Clock/Control from TTC

Output Links to GCT

Crate Output to DAQ

Hub Controller

Input Card

Input Card

Processing Card

Input Card

TTC/DAQ Card

Input Card

Processing Card

Input Card

Input Card

Processing Card

Input Card

(uTCA form factor)

Corner-sharing

Links to Input

Cards in

other Crates

Φ-sharing Links

to Input Cards In

other Crates

HCAL/ECAL TPGs from oSLB Cards

input card coverage sharing
Input Card Coverage/Sharing

56 towers in η

8 towers/card

Input

Card

0

Input

Card

1

Input

Card

2

Input

Card

3

Input

Card

4

Input

Card

5

Input

Card

6

Crate N+1

Input

Card

0

Input

Card

1

Input

Card

2

Input

Card

2

Input

Card

3

Input

Card

4

Input

Card

5

Input

Card

6

Crate N

12 towers/crate

72 towers in φ

Input

Card

0

Input

Card

1

Input

Card

2

Input

Card

3

Input

Card

4

Input

Card

5

Input

Card

6

Crate N-1

slhc rct input card 12 8
SLHC RCT Input Card (12η × 8φ)

Frontpanel

(Serial Links)

Backplane

Microcontroller

(Mezzanine)

Ethernet

HF TPG (1)

η-sharing (6)

HCAL TPG (12)

FPGA

Link

Switch

ECAL TPG (12)

To Proc. Card (~12)

Corner-sharing (4)

To DAQ Card (1-2)

Fast Buffer SRAM

Clock

Circuitry

φ-sharing (4)

Clock and Ctrl

slhc rct processing card 20 12
SLHC RCT Processing Card(~20η × 12φ)

Frontpanel

(Serial Links)

Backplane

Microcontroller

(Mezzanine)

Ethernet

FPGA

From Input Cards

(~30)

Link

Switch

Output to GCT

To DAQ Card (1-2)

Fast Buffer SRAM

Clock

Circuitry

Clock and Ctrl

slhc rct ttc daq card evolution of uw gct aux card
SLHC RCT “TTC”/DAQ Card(Evolution of UW GCT Aux Card)

Frontpanel

Backplane

Microcontroller

(Mezzanine)

Ethernet

DAQ

Xmt

Interface

To DAQ

DAQ Data from

Input and Proc.

Cards (10-20)

FPGA

To TTS

Clock/Control

From TTC

Clock and Control

To Input and

Proc. Cards

TTC Interface

slhc rct key points
SLHC RCT Key Points:
  • Double-width AMC-style (uTCA) modules (148.8mm height, 181.5mm deep)
  • 3 Card Types: Input Card, Processing Card, TTC/DAQ Card (evolution of UW GCT aux card, possibly common card)
    • Input Card receives HCAL/ECAL TPGs, performs inter-region data sharing needed by algorithms (7 cards/crate)
    • Processing card receives partial products from Input Cards, completes regional processing, delivers output to GCT (~3 cards/crate)
    • TTC/DAQ interfaces crate to the TTC and DAQ systems (1/crate)
  • Single Crate Encompasses Full 56-tower η Width
  • Card microcontroller implemented as a Mezzanine
    • Can perform uTCA arbitration if needed
    • High-performance I/O interface to card for Trigger Supervision functions
    • Single hardware/firmware implementation
  • Backplane contains combination of passive and switched interconnections
    • Passive good choice for η-sharing
    • Switches for some routing between Input and Processing cards
  • TPG Inputs are fundamentally compatible with the envisioned upgrade path
    • Affects link and pipeline clock frequency choices
  • Goal is to have a single firmware image for each card type, and to configure individual cards via RAM
slhc cal trig prototype r d platform for conceptual design
SLHC Cal. Trig Prototype(R&D Platform for Conceptual Design)

Microcontroller

(Mezzanine)

GTX Links (6)

SNAP 12 Transceiver (6X/6R)

Ethernet

FPGA

(e.g., Xilinx

XC5VTX240T)

GTX Links (6)

SNAP 12 Transceiver (6X/6R)

Link

Switch

GTX Links (12)

GTX Links (6)

SNAP 12 Transceiver (6X/6R)

Fast Buffer SRAM

Link Clock

Conditioning

Circuitry

Clock and Ctrl

slhc cal trig prototype
SLHC Cal. Trig Prototype
  • R&D Hardware Platform
    • Prove layout/PCB fabrication concepts and principal technologies for Input and Processing cards
    • Circuit Prototypes:
      • Microcontroller Mezzanine Concept
      • Link/Pipeline Clock Conditioning
      • External SRAM/FPGA Interface
  • Double-size AMC module (149mm x 182mm)
  • Suitable for trigger algorithm development
  • Capable of supporting hardware/firmware/system R&D for multiple years