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Digital System Design. Lecture # 01. Who am I?. Engr. Naveed Khan Baloch Lecturer CPED, UET Taxila Office hours: 02:30PM-03:30PM, Background: MSc Computer Engineering Research areas: Current: Processor Design, DSP Processors, FPGA

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Who am i
Who am I?

Engr. Naveed Khan Baloch

Lecturer

  • CPED, UET Taxila

  • Office hours: 02:30PM-03:30PM,

  • Background:

    • MSc Computer Engineering

  • Research areas:

    • Current: Processor Design, DSP Processors, FPGA

    • Other: Embedded Systems, RFID, Web Development, Image acquisition, Pattern Matching


Welcome
Welcome!

  • Engineering

    • Designing, building and testing systems

    • Fast-moving, practical

  • This semester: computers

    • Learn how computers represent information

    • How computers perform computations

    • FPGA implementation of Digital Design

  • Impress your friends and family!


Computer engineering
Computer Engineering

  • Hardware System Design

  • Development

  • Interfacing

  • Software Design, Programming

  • Testing

  • Verification

  • Why do you want to be an engineer?


Simplest model
Simplest Model

CPU

Input

Output

Memory


Technology trends moore s law
Technology Trends: Moore’s Law

Moore’s Law

2X transistors/Chip Every 1.5 years

Called “Moore’s Law”

Gordon Moore (co-founder of Intel) predicted in 1965 that the transistor density of semiconductor chips would double roughly every 18 months.

Microprocessors have become smaller, denser, and more powerful.



Digital system design

Course Contents

Introduction to Digital design

Verilog Basics (Language Specification + Model Sim Introduction and demo)+test bench (Quiz)

Combinational Logic revision and Verilog description (Assignment)

Sequential Logic revision and Verilog description (Quiz)

Design Examples of digital designs with Verilog coding (Assignment)

FPGA Introduction, workshop on Xilinix tools, Spartan 3AN working examples Synthesis---1 (Quiz) (Assignment)

Synthesis---2 (MID)


Digital system design

Course Contents

9. ASMD Introduction Traffic Light Controller + Timers (Assignment)

10. ASMD based UART , TX and RX (Quiz)

11. ASMD based 8-bit RISC processor Design Datapath and Control Unit (Assignment)

12. Addition Architectures (Quiz)

13. Multiplication Architectures (Assignment)

14. Time shared and pipelined architecture

15. Design of floating point unit / VLIW and superscalar architecture

16. DSP using Digital Design (Final)


Course administration
Course Administration

  • Instructor: Engr. NaveedKhan Baloch

  • Lab Teacher: Engr. Nosheena + EngrAsim

  • Labs: Digital Systems

  • Group: ???

  • Course Email: naveed.khan@uettaxila.edu.pk


Grading
Grading

  • Rough Grade Breakdown

    • Quizzes + Assignments 10%MID Semester Exam 20%End Semester Exam 40%

    • Lab + Mini Project 30%

      Project Report

      Demo

      Lab Reports


Class schedule
Class Schedule

  • Class Time and Day: Tuesday

  • (08:40 AM to 11:10 AM) 2k9

  • Venue: Computer Department

  • Class Room # 03


Homework and projects
Homework and Projects

  • Due before class every Wednesday

    • Time for assignment = 1 Week

  • Easiest way to get a good grade in DSD

    • Come to class and do the homework

  • Mini project

    • Demo on FPGA

    • Verilog based Simulation on Modelsim


Reading material
Reading Material

Text Book

  • Advanced Digital Design with Verilog HDL by Michael D. Ciletti, Edition 2004 or Latest, Prentice Hall.

    Reference Books

  • Verilog HDL-A guide to digital design and synthesis by Samir Palnitkar, 2nd Edition, Prentice Hall Publisher

  • Lecture Slides

  • Reading material