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Digital System Design. Course Introduction. Maziar Goudarzi. Course Outline. Course contents Verilog HDL ® Design Methodology Programmable Logic Devices Course timing Will be put on the Courseware page Teaching Assistants As announced Exercise classes

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Digital system design

Digital System Design

Course Introduction

Maziar Goudarzi


Course outline
Course Outline

  • Course contents

    • Verilog HDL®

    • Design Methodology

    • Programmable Logic Devices

  • Course timing

    • Will be put on the Courseware page

  • Teaching Assistants

    • As announced

  • Exercise classes

    • Sunday or Tuesday 12-13, Place: TBA

DSD


Textbook and references
Textbook and References

  • Textbook

    • SamirPalnitkar, Verilog® HDL: A Guide to Digital Design and Synthesis, Second Edition, Prentice Hall PTR, 2003.

    • ZoranSalcic, AsimSmailagic, Digital System Design and Prototyping Using Field Programmable Logic and Hardware Description Languages, Kluwer Academic Publishers, 2002.

  • Other references

    • Pong P. Chu, FPGA Prototyping by Verilog Examples, Wiley, 2008.

    • J. Bhaskar, Verilog HDL Synthesis: A Practical Primer, Star Galaxy Publishing, 1998.

    • Chan, Mourad, Digital Design Using Field Programmable Gate Arrays, Prentice Hall PTR, 1994.

    • Verilog HDL, IEEE 1364-2005 Standard, IEEE Computer Society, Design Automation Standards Committee, 2006.

DSD


Evaluation
Evaluation

  • 50% or more Assignments and Course Project

  • 25% Midterm exam

  • 25% Final exam

DSD


Digital system design1

Digital System Design

Introduction to Hardware Description Languages


Digital system
Digital System

  • System

  • Digital vs. Analog

DSD


Why hdl evolution of logic design
Why HDL? Evolution of Logic Design

  • Early days

    • 10s of logic gates

DSD


Evolution of logic design cont d
Evolution of Logic Design (cont’d)

  • A decade later

    • 100s of logic gates

    • Schematic design

  • Another decade later

    • 1000s of logic gates

    • Structural Hardware Description Languages (HDL)

  • State of the art

    • 10,000s-1000,000s-10,000,000s logic gates

    • Behavioral and Register Transfer Level HDL

DSD



Why hdls
Why HDLs?

  • SSI (Small Scale Integration)

  • MSI (Medium Scale Integration)

  • LSI (Large Scale Integration)

  • VLSI (Very Large Scale Integration)

  • Important concepts

    • Simulation = check if design works fine

    • Synthesis = implement the design on real hardware

DSD


Hdl requirements
HDL Requirements

  • Concurrency

  • Timing and Delay

  • Event-driven

  • Design Hierarchy

  • Implementation independence

  • Readability (Documentation)

DSD


Popular levels of abstraction
Popular Levels of Abstraction

Behavioral

problem

Data flow

Structural

Switch

DSD


Popular levels of abstraction cont d
Popular Levels of Abstraction (cont’d)

Behavioral

problem

Data flow

Structural

Switch

DSD


Popular levels of abstraction cont d1
Popular Levels of Abstraction (cont’d)

Behavioral

problem

Data flow

Structural

Switch

DSD


Popular levels of abstraction cont d2
Popular Levels of Abstraction (cont’d)

Behavioral

problem

Data flow

Structural

Switch

DSD


Hdl examples
HDL Examples

  • AHDL

    • Altera HDL

  • CDL: Computer Description Language

    • 1965

  • ISPS: Instruction Set Processor Specification

  • AHPL: A Hardware Programming Language

  • Abel

    • Small designs such as state machines

DSD


Verilog hdl
Verilog HDL

  • Verifying Logic

  • Phil Moorby from Gateway Design Automation in 1984 to 1987 (absorbed by Cadence)

  • Verilog-XL Simulator from GDA in 1986

  • Synopsys synthesis tool in 1988

  • In 1990 became open language, OVI (Open Verilog International)

  • IEEE standard 1995

  • Similar to C

  • Fairly efficient and easy to write

DSD


VHDL

  • VHSIC HDL: Very High Speed Integrated Circuit Hardware Description Language

  • DARPA workshop on VHSIC in 1981

  • DARPA released requirement in 1983

  • A language for hardware documentation

  • VHDL 7.2 in 1985

  • IEEE standard in 1987

  • ANSI standard in 1988

  • For RTL design VITAL added,

    • VITAL(VHDL Initiative Towards ASIC Library)

  • IEEE revised VHDL & VITAL in 1993

  • Final review of standard in 2001

  • Similar to Ada (emphasis on re-use and maintainability)

  • Very general, but verbose

DSD


Hello world vhdl vs verilog
Hello World! VHDL vs. Verilog

VHDL

Verilog

//-----------------------------------------------------

// This is my first Verilog Program

// Design Name : hello_world

// File Name : hello_world.v

// Function : This program will print 'hello world‘

// Coder : Deepak

//-----------------------------------------------------

modulehello_world ;

initial begin

$display ("Hello World by Deepak");

#10 $finish;

end

endmodule// End of Module hello_world

------------------------------------------

-- Design Name : hello_world

-----------------------------------------

entityhello_worldis

end;

architecturehello_worldofhello_worldis

begin

stimulus : process

begin

assert false report "Hello World By Deepak“

severity note;

wait;

endprocess stimulus;

endhello_world;

DSD

Ref: www.asic-world.com


Vhdl vs verilog
VHDL vs. Verilog

  • All abstraction levels

  • Designed for documentation

  • Ada based constructs

  • High level & system descriptor

  • No PLI

  • All abstraction levels

  • Designed for hardware design

  • C and Ada constructs

  • Gate & structural descriptor

  • Very powerful PLI

DSD


Vhdl vs verilog1
VHDL vs. Verilog

Behavioral

Dataflow

VHDL

Verilog

Structural

& Gate

Switch

DSD


Vhdl vs verilog2
VHDL vs. Verilog

  • VHDL, More popular in Europe

  • Verilog, In USA, Japan

DSD


Announcement
Announcement

  • اولین دوره کشوری مسابقه طراحی سیستمهای دیجیتال

    • مسابقه دو به دو بین طرحهای سخت افزاری

    • مسابقه طراحی شتاب دهنده برای یک الگوریتم رمزگذاری

      http://fpgasoc.ir

  • FPT’2013 Design Contest

    • Design hardware for a Game

    • Designs compete against one another in a live contest

      http://lut.eee.u-ryukyu.ac.jp/dc13/

  • ModelSim Getting Started class

    • Next Sunday (time and place to be announced)

    • Software link will be provided

    • Bring your laptop if any

DSD


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