Digital System Design

1. Digital System Design Verilog® HDLUseful Modeling Techniques Maziar Goudarzi

2. Today Program • Procedural Continuous Assignment • Overriding Parameters • Conditional Compilation and Execution • Useful System Tasks Verilog HDL

3. Procedural Continuous Assignment Useful Modeling Techniques

4. Procedural Continuous Assignment • Overrides, for a certain time, the effect of regular assignments to a variable. • Two types • assign/deassign • Works only on register data types • force/release • Works on both register and net data types • Note: • Not synthesizable. Use only for modeling and simulation Verilog HDL

5. Procedural Continuous Assignment (cont’d) • assign/deassign • Keywords • assign: overrides regular procedural assignments • LHS: reg or concatenation of regs. No nets. No arrays. No bit-select or part-select • deassign: re-enables regular procedural assignments • After deassign: • Last value remains on the register until a new procedural assignment changes it. Verilog HDL

6. Verilog HDL

7. Procedural Continuous Assignment (cont’d) • force/release • Keywords: • force: overrides all procedural/continuous/ procedural continuous assignments • release: re-enables other assignments • Hence, assignments in priority order: 1. force 2. assign (procedural continuous) 3. Procedural/continuous assignments Verilog HDL

8. force/release on reg variables Verilog HDL

9. force/release on nets • Net value immediately returns to its normal assigned value when released Verilog HDL

10. Overriding Parameters Useful Modeling Techniques

11. Overriding Parameters • Two methods • defparam statement • Module instance parameter value assignment • defparam statement • Keyword: defparam • Syntax: defparam <parameter_hierarchical_name>=<value>; Verilog HDL

12. Verilog HDL

13. Overriding Parameters (cont’d) • Module instance parameter values • Parameters are overridden when the module is instantiated • Syntax: <module_name> #(<param_vals>) <instance_name>; Verilog HDL

14. Example with multiple parameters Verilog HDL

15. Conditional Compilation and Execution Useful Modeling Techniques

16. Conditional Compilation • Usage: • To compile some part of code under certain conditions • Keywords: • ‘ifdef, `else, `endif • ‘define to define the flag Verilog HDL

17. Verilog HDL

18. Conditional Execution • Usage: • To execute some part of code when a flag is set at runtime • Used only in behavioral modeling • Keywords: • $test$plusargs • Syntax: • $test$plusargs( <argument_to_check> ) Verilog HDL

19. Verilog HDL

20. Useful System Tasks Useful Modeling Techniques

21. Useful System TasksFile Output • Opening a file • Syntax: <file_handle> = $fopen( “<file_name>” ); • <file_handle>is a 32 bit value, called multi-channel descriptor • Only 1 bit is set in each descriptor • Standard output has a descriptor of 1 (Channel 0) Verilog HDL

22. Useful System TasksFile Output (cont’d) • Writing to files • $fdisplay, $fmonitor, $fstrobe • $strobe, $fstrobe • The same as $display, $fdisplay, but executed after all other statements schedule in the same simulation time • Syntax: $fdisplay(<handle>, p1, p2,…, pn); • Closing files $fclose(<handle>); Verilog HDL

23. Example: Simultaneously writing to multiple files Verilog HDL

24. Useful System TasksRandom Number Generation • Syntax: $random; $random(<seed>); • Returns a 32 bit random value Verilog HDL

25. Useful System TasksInitializing Memory from File • Keywords: • $readmemb, $readmemh • Used to initialize memory (reg [3:0] mem[0:1023]) • Syntax: $readmemb(“<file_name>”, <memory_name>); $readmemb(“<file_name>”, <memory_name>, <start_addr>); $readmemb(“<file_name>”, <memory_name>, <start_addr>, <finish_addr>); • The same syntax for$readmemh Verilog HDL

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27. Useful System TasksValue Change Dump (VCD) File • ASCII file containing information on • Simulation time • Scope and signal definitions • Signal value changes • Keywords • $dumpvars • $dumpfile • $dumpon • $dumpoff • $dumpall Verilog HDL

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29. Today Summary • Introduced a number of modeling techniques useful in various applications Verilog HDL

30. Other Notes • Homework 8 • Chapter 9: • All exercises with ModelSim, except for 3 and 5 • 3 and 5 in paper and pencil • Due date: Sunday, Day 11th Verilog HDL