VLSI Digital System Design

1. Clocking VLSI Digital System Design

2. Q D logic Q D Clocked System • Basic structure clock

3. Fundamental Timing Parameters • Positive edge-triggered flip-flop clock D Q

4. Static Storage Elements • Level-sensitive latch • Edge-triggered master-slave flip-flop • RS latch • T flip-flop • JK flip-flop

5. Level-Sensitive Latch 0 D 0 Q Q 1 D 1 clock clock Positive level-sensitive latch Negative level-sensitive latch

6. Positive Edge-TriggeredMaster-Slave Flip-Flop 0 0 D Q 1 1 clock clock Master stage Slave stage

7. RS Latch R R Q Q ~Q ~Q S S

8. RS Latch Behavior • S R Q • 0 0 Maintain previous state • 0 1 0 • 1 0 1 • 1 1 Undefined

9. Incorrect T Flip-Flop Q 0 0 1 1 clock clock ~clear

10. JK Flip-Flop Behavior • J K Q • 0 0 Maintain previous state • 0 1 0 • 1 0 1 • 1 1 Toggle

11. Level-Sensitive Latch Circuit clock 0 ~clock Q Q 1 ~clock D D clock clock Level-sensitive latch Level-sensitive latch circuit

12. Jamb Latch Circuit clock weak ~clock Q ~Q ~clock ~clock D D clock clock Level-sensitive latch circuit Jamb latch circuit

13. Jamb Latch Circuit Design • Replace feedback transmission gate with: • Feedback inverter that is weaker thandriving inverter • Either: Decrease gain of feedback transistors • Increase L to decrease W/L • Or: Increase gain of driving inverter

14. Level-Sensitive Latch Circuit clock Q ~clock clock ~clock D Q ~clock ~clock clock D clock Level-sensitive latch circuit Redrawn level-sensitive latch circuit

15. BufferedLevel-Sensitive Latch Circuit Q Q ~clock ~clock clock clock D D clock ~clock ~clock clock Buffered level-sensitive latch circuit Redrawn level-sensitive latch circuit

16. Detailed BufferedLevel-Sensitive Latch Circuit Q Q ~clock ~clock clock clock D D clock ~clock ~clock clock Buffered level-sensitive latch circuit Buffered level-sensitive latch circuit, details

17. Simplified BufferedLevel-Sensitive Latch Circuit Q Q ~clock clock ~clock clock D D ~clock clock ~clock clock Buffered level-sensitive latch circuit Buffered level-sensitive latch circuit, with one connection deleted

18. Dynamic Latches • Time before refresh required depends upon leakage current • Leakage current depends upon temperature • Refresh even if behavior independent of stored value • Intermediate voltage level causesdriven gates to draw current

19. Q D Inputpad R C Clock Skew clock

20. Q D Inputpad R C PLL Phase-Locked Loop clock

21. Q D Inputpad R C Div by 4 PLL Higher On-Chip Clock Frequency clock

22. Div by 4 PhaseDetector ChargePump Filter VoltageControlledOscillator (VCO) Phase-Locked Loop Block Diagram 4 * fin Reference clock fin

23. Probability of Upset • Upset is the case of a storage element resolving to the wrong data value • p = probability of upset = T0 exp( - tr/tc ) • T0 = constant for the circuit design • tc = time constant of resolution for the element = 1/GB = 1/(gain-bandwidth product) = constant for the circuit design

24. Resolve Time, tr • p = probability of upset = T0 exp( - tr/tc ) • tr = resolve time = time allowed for the storage element to resolve its state

25. Probability of Upset Example • T0 = 0.1 s • tc = 0.1 ns • tr = 5.0 ns • p = T0 exp( - tr/tc ) = 0.1 * exp( -5.0/0.1 ) = 0.1 * exp( -50 ) = 0.1 * 1.9 * 10-22 = 1.9 * 10-23 Hz-1Hz-1s-1

26. Mean Time Between Upsets • MTBU = 1/( p * fc * fd ) • p = probability of upset = T0 exp( - tr/tc ) • fc = clock frequency • fd = data frequency

27. MTBU Example • p = 1.9 * 10-23 Hz-1Hz-1s-1 • fc = 100 MHz • fd = 1 Mhz • MTBU = 1/( p * fc * fd ) = 1/( 1.9 * 10-23 * 108 * 106 ) = 1/( 1.9 * 10-9 ) = 5.2 * 108 s = 16.4years

28. MTBU Perspective • May have thousands of storage elementsin a system • May have thousands or millions of systems • Provide margin of safety • Maximize resolve time, tr

29. Q D Q D Synchronizer asynchronous data synchronized data clock