1 / 19

Computer Organization & Assembly Language

Computer Organization & Assembly Language. Lecture # 10 By Muhammad Jafer. CENTERAL PROCESSING UNIT. Register Set Athematic Logic Unit Control Unit Data path. Instruction Cycle. Instruction Register. DATA PATH. Capable of performing certain operation on data Athematic Logic Unit

thimba
Download Presentation

Computer Organization & Assembly Language

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Computer Organization & Assembly Language Lecture # 10 By Muhammad Jafer

  2. CENTERAL PROCESSING UNIT • Register Set • Athematic Logic Unit • Control Unit • Data path

  3. Instruction Cycle • Instruction Register

  4. DATA PATH • Capable of performing certain operation on data • Athematic Logic Unit • External Busses & Internal Busses • Both can have different design

  5. One-bus organization • Single Bus • One instruction fetching per CPU cycle • Simple & Cheapest • Slow

  6. two-bus organization • two Bus • Two instruction fetching per CPU cycle • In-bus & Out-bus design

  7. three-bus organization • Three Bus • Two In-bus & one Out-bus design • More busses will have data transfer faster • More complex hardware design • Expensive

  8. Instruction Cycle EXAMPLES • MOV AL,5 • ADD AL,[003]

  9. Complex Instruction Cycle

  10. Interrupts • Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing • Program • e.g. overflow, division by zero • Timer • Generated by internal processor timer • Used in pre-emptive multi-tasking • I/O • from I/O controller • Hardware failure • e.g. memory parity error

  11. IF Interrupts • Suspend execution of current program • Save context • Set PC to start address of interrupt handler routine • Process interrupt • Restore context and continue interrupted program

  12. IF Interrupts

  13. IF Interrupts • Suspend execution of current program • Save context • Set PC to start address of interrupt handler routine • Process interrupt • Restore context and continue interrupted program

  14. Program TimingShort I/O Wait

  15. Program TimingLONG I/O Wait

  16. Control unit • Part of CPU • Management of Computer Resources • Control and Timing Signals • Directs Flow of Data • CU Types • Mircoprogrammed • Hardwire

  17. MICROPROGRAMMED • Memory Units storing Control Signals • Inaccessible Memory Units in RAM or ROM • Control Word is microinstruction • Microinstruction = 1/More Microoperations • Sequence of microinstructions are microprograms

  18. hardwired • Fixed Logical Instructions • Far more faster • Not cheaper & Complex

  19. Chapter Review • Fundamentals of Computer Organization and Architecture by MostafaAbd-Al-Barr & HeshamAlRewini • Chapter # 5 • CPU Basics • Register Set • Datapath • CPU Instruction Cycle • Control Unit

More Related