1 / 63

1.69k likes | 4.26k Views

Analog-to-Digital and Digital-to-Analog Conversion. Introduction (Applications and S/H Circuit) DAC ADC. Computerized Motor Control Through the Use of a DAC . Example: Function Generator Using a ROM and a DAC. Low Pass Filter. T SIGNAL. T CLK.

Download Presentation
## Analog-to-Digital and Digital-to-Analog Conversion

**An Image/Link below is provided (as is) to download presentation**
Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.
Content is provided to you AS IS for your information and personal use only.
Download presentation by click this link.
While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.
During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

**Analog-to-Digital and Digital-to-Analog Conversion**• Introduction (Applications and S/H Circuit) • DAC • ADC ECE 3450 M. A. Jupina, VU, 2014**Computerized Motor Control Through the Use of a DAC**ECE 3450 M. A. Jupina, VU, 2014**Example: Function Generator Using a ROM and a DAC**Low Pass Filter TSIGNAL TCLK ECE 3450 M. A. Jupina, VU, 2014**What clock frequency will result in a 100 Hz sine wave at**the output? What method could be used to vary the peak-to-peak amplitude of the sine wave? Adjust the reference voltage of the DAC. ECE 3450 M. A. Jupina, VU, 2014**Programmable Gain Amplifier with a DAC**AC Input Signal DC Input Signal Digital Inputs IO AC Output Signal IO DC Blocking Capacitor ECE 3450 M. A. Jupina, VU, 2014**DVM Using an ADC**ECE 3450 M. A. Jupina, VU, 2014**Real World Applications**Analog-to-digital converters (ADC) and digital-to-analog converters (DAC) are used to interface a computer to the analog world so that the computer can monitor and control a physical variable. ECE 3450 M. A. Jupina, VU, 2014**Data Sampling System Block Diagram**ECE 3450 M. A. Jupina, VU, 2014**Simplified Diagram of a Sample-and-Hold Circuit**ECE 3450 M. A. Jupina, VU, 2014**LF398 Sample-and-Hold (S/H) Circuit**mF ECE 3450 M. A. Jupina, VU, 2014**Generation of the S/H Control Input Signal on UP1 Board**ECE 3450 M. A. Jupina, VU, 2014**Block Diagram of a Digital Storage Oscilloscope**ECE 3450 M. A. Jupina, VU, 2014**Digital Signal Processor (DSP) Architecture**ECE 3450 M. A. Jupina, VU, 2014**Digital Filter (FIR Low Pass) Implementation on UP1 Board**Ideal FIR LP Filter ECE 3450 M. A. Jupina, VU, 2014**Example Filter Measurements on a Scope**ALL Pass Filter (Sampling Effects) ALL Pass Filter (Alias Signal) FIR Low Pass Filter (Gain and Phase Measurements) Vinpp Voutpp Df ECE 3450 M. A. Jupina, VU, 2014**Digital-to-AnalogConversion**Definitions Example Problems Various DAC Circuitries DAC0808 ECE 3450 M. A. Jupina, VU, 2014**Four-Bit DAC with Voltage Output**VREF = 16 V ECE 3450 M. A. Jupina, VU, 2014**Output Waveform of a 4-Bit DAC with a Binary Counter**Supplying the Input ECE 3450 M. A. Jupina, VU, 2014**DAC Transfer Function**ECE 3450 M. A. Jupina, VU, 2014**Definitions**• Full Scale Output – the maximum value that the D/A converter can produce. • Resolution or Step Size – the smallest change that can occur in the analog output as a result of a change in the digital input. where N is number of bits • Analog Output= K • decimal value of the digital input • Percentage Resolution • Accuracy • Full Scale Error – maximum deviation of the DAC’s output from its ideal value. • Linearity Error – maximum deviation in step size from the ideal step size. • Offset Error – the small output voltage that exists when all inputs are “0” • Settling Time – the time required for the DAC output to go from zero to full scale as the binary input goes from all 0’s to all 1’s. ECE 3450 M. A. Jupina, VU, 2014**Example Problems**• An eight-bit DAC produces an output voltage of 2.0 V for an input code of 01100100. What will the value of VOUT be for an input code of 10110011? 011001002 = 10010 101100112 = 17910 (179/100) = (X/2V) X = 3.58V • What is the resolution of the DAC in the previous? Express it in volts and as a percentage. Determine the weight of each input bit. Resolution = 2V/100 = 20mV Full Scale Voltage = 20mV (28 -1) = 5.1V % Resolution = [20mV / {20mV (28 -1) }] x 100% 0.4% LSB = 2V/100 = 20mV Other bits: 40mV, 80mV, 160mV, 320mV, 640mV, 1280mV, and 2560mV. ECE 3450 M. A. Jupina, VU, 2014**Example Problems**• What is the resolution in volts of a 10-bit DAC whose Full-Scale output is 5 V? 10 bits---> 210 -1 = 1023 steps Resolution = 5V/1023 = 4.89 mV 5mV • How many bits are required for a DAC so that its Full-Scale output is 10 mA and its resolution is less than 40 mA? The maximum resolution is 40µA. The number of steps required to produce 10mA full scale will be at least 10mA/40µA = 250. Therefore, it requires at least 8 bits. ECE 3450 M. A. Jupina, VU, 2014**Example Problems**• Assuming a 12-bit DAC with perfect accuracy, how close to 250 rpm can the motor speed be adjusted for the motorized system below? 12-bit DAC gives us 212 -1 steps = 4095. Step-Size = 2mA/4095 = 488.4nA To have exactly 250 RPM the output of the DAC must be (250 RPM x 2mA) / 1000 RPM = 500µA. In order to have 500µA at the output of the DAC, the computer must increment the input of the DAC to the count of 500µA/488.4nA = 1023.75. Thus, the motor will rotate at (1024/4095) x 1000 RPM = 250.061 RPM when the computer's output has incremented 1024 steps. ECE 3450 M. A. Jupina, VU, 2014**Example Problems**• An eight-bit DAC has a full-scale error of 0.2% F.S. If the DAC has a full-scale output of 10 mA, what is the most that it can be in error for any digital input? If the DAC output reads 50 mA for a digital input of 00000001, is this within the specified range of accuracy? (Assume no offset error.) Full Scale error = 0.2% x 10mA = 20µA Step-Size = 10mA/255 = 39.2µA. Ideal output for 000000012 is 39.2µA. The possible range is 39.2µA ± 20µA = 19.2µA to 59.2µA. Thus, 50µA is within this range. ECE 3450 M. A. Jupina, VU, 2014**Example Problems**• A particular 6-bit DAC has a full-scale output rated at 1.260 V. Its accuracy is specified as ± 0.1% F.S., and it has an offset error of ±1 mV. Assume that the offset error has not been zeroed out. Consider the measurements made on this DAC in the table below, and determine which of them are not within the device’s specifications. Step-Size = 1.26V/63 = 20mV ±0.1% F.S. = ±1.26mV Thus, maximum error will be ±1.26mV ±1mV = ±2.26 mV. 0000102 --> 2 x 20mV = 40mV [41.5mV is within specs.] . 0001112 --> 7 x 20mV = 140mV [140.2mV is within specs.] . 0011002 --> 12 x 20mV = 240mV [242.5mV isn't within specs.] . 1111112 --> 63 x 20mV = 1.260V [1.258 V is within specs.] . ECE 3450 M. A. Jupina, VU, 2014**Simple DAC Using an Op-Amp Summing Amplifier with**Binary-Weighted Resistors 1 KW 1 KW 2 KW 4 KW 8 KW ECE 3450 M. A. Jupina, VU, 2014**Improved DAC using Summing Amplifier with Precision Voltage**Source 1 KW 1 KW 2 KW 4 KW 8 KW ECE 3450 M. A. Jupina, VU, 2014**Basic R/2R Ladder DAC**ECE 3450 M. A. Jupina, VU, 2014**DAC0808 R/2R Ladder DAC with Current Output**ECE 3450 M. A. Jupina, VU, 2014**DAC0808 Block Diagram**ECE 3450 M. A. Jupina, VU, 2014**DAC0808 Specifications**• The DAC0808 is an 8-bit monolithic DAC • Full Scale Error: ±0.19% • Offset current levels less than 4 mA for • Maximum output current: 2 mA. • Fast settling time: 150 ns typical • Power supply voltage range: ±4.5V to ±18V • Low power consumption: 33 mW @ ±5V ECE 3450 M. A. Jupina, VU, 2014**DAC Circuit**MSB LSB ECE 3450 M. A. Jupina, VU, 2014**Analog-to-DigitalConversion**Definitions Effects of Sampling Various ADC Circuitries Example Problems ADC0804 ECE 3450 M. A. Jupina, VU, 2014**General Diagram of One Class of ADCs**ECE 3450 M. A. Jupina, VU, 2014**Typical Computer Data Acquisition System**Waveforms showing how the computer initiates each new conversion cycle and then loads the digital data into memory at end of conversion (EOC). ECE 3450 M. A. Jupina, VU, 2014**ADC Ideal Linear Transfer Function**ECE 3450 M. A. Jupina, VU, 2014**Definitions**• Full Scale Input – the maximum value that the A/D converter can accept. • Resolution or Step Size – the smallest change that can occur in the analog input to produce a change in the digital output. where N is number of bits • Accuracy • Quantization Error – the maximum difference between the actual analog input voltage and the digital output value representing it. This is equal to the resolution. • Full Scale Error – maximum deviation in the ADC’s comparator reference voltage or the internal DAC’s output voltage from the ideal value. • Conversion Time – the time required for the ADC to convert an analog input voltage into a digital output. ECE 3450 M. A. Jupina, VU, 2014**Digitizing an Analog Signal**ADC DAC LPF fed through a DAC ECE 3450 M. A. Jupina, VU, 2014**Nyquist Criterion**In order to avoid loss of information, the incoming signal must be sampled at a rate greater than two times the highest frequency component in the incoming signal. Example: CD Audio, FSAMPLING = 44 KHz since FMAX = 22 KHz A signal alias is produced by sampling the signal at a rate less than the minimum rate (twice the highest frequency). ECE 3450 M. A. Jupina, VU, 2014**An Alias Signal Due to Under-Sampling**Sine wave frequency is 1.9 KHz. This signal is sampled every 500 ms (FSAMPLING = 2 KHz). Data samples are indicated by square dots. These square dots form a sinusoidal waveform with a period of 10 ms or a frequency of 100 Hz.. The alias frequency is the difference between the sampling frequency and the frequency of the incoming signal. ECE 3450 M. A. Jupina, VU, 2014**Digital-Ramp ADC**ECE 3450 M. A. Jupina, VU, 2014**Three-Bit Flash ADC**3 KW 1 KW 1 KW 1 KW 1 KW 1 KW 1 KW 1 KW ECE 3450 M. A. Jupina, VU, 2014**Four-Bit Successive-Approximation ADC**ECE 3450 M. A. Jupina, VU, 2014**Example Problems**• An eight-bit digital ramp ADC with a 40 mV resolution uses a clock frequency of 2.5 MHz. Determine the following values: • the digital output for an analog voltage of 6.005 V • the digital output for an analog voltage of 6.035 V • the maximum and average conversion times • 6.005 V / 40 mV = 150.125 = 15110 = 100101112. • Using same method as in (a) the digital value is again 100101112. • Maximum conversion time = (max. # of steps) x (TCLOCK) tmax_conv = (28-1) x (0.4µs) = 102µs. Average conversion time = 102µs/2 = 51µs ECE 3450 M. A. Jupina, VU, 2014**Example Problems**• Why were the digital outputs the same for parts a) and b) of question 1? Because the difference in the two values of VA was smaller than the resolution of the converter. ECE 3450 M. A. Jupina, VU, 2014**Example Problems**• An ADC has the following characteristics: resolution of 12 bits, full scale error of 0.03%, and full scale input of 5 V. What is the quantization error in volts? What is the total possible error in volts? With 12 bits, percentage resolution is (1/(212-1)) x 100% = 0.024%. Thus, quantization error = 0.024% x 5V = 1.2mV. Error due to 0.03% inaccuracy is 0.03% x 5V = 1.5mV. Total Error = 1.2mV + 1.5mV = 2.7mV. ECE 3450 M. A. Jupina, VU, 2014**Example Problems**• A data acquisition system is being used to digitize an audio signal. The sampling frequency is 20 KHz. Determine the output frequency that will be heard for each of the following input frequencies? • 5 KHz < FMAX, 5 KHz • 10.1 KHz > FMAX, 9.9 KHz • 10.2 KHz > FMAX, 9.8 KHz • 15 KHz > FMAX, 5 KHz • 19.1 KHz > FMAX, 900 Hz • 19.2 KHz > FMAX, 800 Hz ECE 3450 M. A. Jupina, VU, 2014**Example Problems**• The figure below shows the waveform at VAX for a 6-bit successive approximation ADC with a step size of 40 mV during a complete conversion cycle. Examine this waveform and describe what is occurring at times t0 to t5. Then determine the resultant digital output. ECE 3450 M. A. Jupina, VU, 2014**Example Problems**Full scale input = (26-1) 40mV = 2.52V t0: Set MSB (bit 5); t1: Set bit 4; clear bit 4; t2: Set bit 3; clear bit 3; t3: Set bit 2; t4: Set bit 1; clear bit 1; t5: Set LSB; Digital result = 1001012 = 3710 Thus 1.48 V < VA < 1.52 V ECE 3450 M. A. Jupina, VU, 2013**ADC0804 Eight-Bit Successive-Approximation ADC with**Tri-State Outputs ECE 3450 M. A. Jupina, VU, 2014

More Related