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NAND & FAT Presentation

NAND & FAT Presentation

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NAND & FAT Presentation

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  1. NAND & FAT Presentation 報告人: 侯欽堅

  2. Outline • NAND Flash SPEC • NAND Flash Controller & Control Code • Look up Table Mechanism • NAND Flash Code Flow • FAT SPEC • FAT Code Flow • FILE Process

  3. NAND Flash Spec – Pin Configuration

  4. NAND Flash Spec – Pin Description

  5. NAND Flash Spec – Array Organization Small BlockK9K1G08U0A Large BlockK9F1G08U0A

  6. NAND Flash Spec – Functional Block Diagram Small Block Large Block

  7. NAND Flash Spec – Address assign Small Block Large Block

  8. NAND Flash Spec – Plane Design Small Block K9K1G

  9. NAND Flash Spec – Plane Design Large Block K9K8GU0M

  10. NAND Flash Spec – Signal Diagram

  11. NAND Flash Spec – Signal Diagram

  12. NAND Flash Spec – Signal Diagram

  13. NAND Flash Spec – Command Set Small Block

  14. NAND Flash Spec – Command & Timing -- Read

  15. NAND Flash Spec – Command & Timing -- Program

  16. NAND Flash Spec – Command & Timing -- Erase

  17. NAND Flash Spec – Command & Timing -- Read ID

  18. NAND Flash Spec – Command Set Large Block

  19. NAND Flash Spec – Command & Timing -- Read

  20. NAND Flash Spec – Command & Timing Random Data Output In a Page

  21. NAND Flash Spec – Command & Timing Page Program Operation with Random Data Input

  22. NAND Flash Spec – Command & Timing (available only within a block) Cache Program Operation After writing the first set of data up to 2112byte into the selected cache registers, Cache Program command (15h) instead of actual Page Program (10h) is inputted to make cache registers free and to start internal program operation.

  23. NAND Flash Spec – Command & Timing -- Copy Back 同一Plane內,可以不用經過外部的Memory,就可以執行資料搬移。 限制: 同奇或同偶

  24. NAND Flash Spec – Command & Timing Copy-Back Operation with EDC & Sector Definition for EDC 功能: If the source page has one bit error due to charge loss or charge gain, then without EDC, the copy-back program operation could also accumulate bit errors. 限制: • To make EDC valid, the page program operation should be performed on either whole page(2112byte) or sector(528byte). • Modifying the data of a sector by Random Data Input before Copy-Back Program must be performed for the whole sector and is allowed only once per each sector.

  25. NAND Flash Spec – Command & Timing Two-Plane Program

  26. NAND Flash Spec – Command & Timing Two-PlaneBlock Erase

  27. NAND Flash Spec – Command & Timing Two-Plane Copy Back

  28. NAND Flash Spec – Command & Timing Interleave Page Program

  29. NAND Flash Spec – Command & Timing Interleave Block Erase

  30. NAND Flash Spec – Command & Timing

  31. NAND Flash Spec – Initial Invalid block

  32. Outline • NAND Flash SPEC • NAND Flash Controller & Control Code • Look up Table Mechanism • NAND Flash Code Flow • FAT SPEC • FAT Code Flow • FILE Process

  33. NAND Flash Controller & Control Code – SPEC APB Slave: This block acts as an interface between APB bus and the smart media card host controller. The APB slave receives the address and data from the APB bus. It decodes the address and writes the data into the control Registers, address FIFO and data FIFO. A. Block Diagram Data FIFO: The data FIFO stores data intended to be written into and read from the memory module. The data does not include spare area data and instead the spare area is automatically generated while performing write operation. Address FIFO: The Address FIFO stores the read / write address which CPU intends to read data from or write data to. The AHB slave pushes the addresses into the address FIFO. Then, the memory interface block pops them and translates them into address latch commands. Control Registers: The Address FIFO stores the read / write address which CPU intends to read data from or write data to. The AHB slave pushes the addresses into the address FIFO. Then, the memory interface block pops them and translates them into address latch commands. Memory Interface Control : The memory interface control block issues commands to the memory modules according to the content of the control registers.

  34. NAND Flash Controller & Control Code – SPEC B. Features

  35. NAND Flash Controller & Control Code – SPEC C. Command Set Support

  36. NAND Flash Controller & Control Code – SPEC D. Register

  37. NAND Flash Controller & Control Code – SPEC D. Register

  38. volatile INT8U xdata PortDMAIAPBControl _at_ 0xF2E5; volatile INT8U xdata PortDMAIAPBAddress _at_ 0xF2E6; volatile INT8U xdata PortDMAIControl _at_ 0xF2EB; NAND Flash Controller & Control Code – APB //a FLASH_CTL register is 32bits width, u8FlashCtlDataReg[4] is used to store it. void vReadFlashCtlReg(INT8U u8addr) { PortDMAIAPBControl = 0x1; //select FLASH_CTL PortDMAIAPBAddress = u8addr; PortDMAIControl = DMAI_CONTROL_APB_RD;//4 }

  39. NAND Flash Controller & Control Code – Code void vWriteFlashCtlReg32(INT8U u8addr, INT32U u32data) { PortDMAIAPBControl = 0x1; //select SMM0 PortDMAIAPBAddress = u8addr; PortDMAIData0 = u32data & 0xFF; PortDMAIData1 = (u32data & 0xFF00) >> 8; PortDMAIData2 = (u32data & 0xFF0000) >> 16; PortDMAIData3 = (u32data & 0xFF000000) >> 24; //highest PortDMAIControl = DMAI_CONTROL_APB_WR; }

  40. Flash Initial Sequence --BOOLEAN bFlashCfgInit() Configuration register

  41. Command Issue Sequence Spare area write data register 0/1 Access Control register Status register

  42. DMA Control Sequence DMA & FIFO register Access Control register

  43. Outline • NAND Flash SPEC • NAND Flash Controller & Control Code • Look up Table Mechanism • NAND Flash Code Flow • FAT SPEC • FAT Code Flow • FILE Process

  44. Look Up table Mechanism • NAND Flash 特性 --- Program之前必須Block Erase 1->0 0->1 • 所以若只Program Block中的部分資料,必須使用以下步驟以避免資料遺失

  45. Look Up table Mechanism • 1 NAND Flash  1Disk  n Zone • 1 Zone = 1024 Physical Block = 1000 Logical Block , 其餘有三功能 • Bad Block 替換用 • 資料搬移用 • 存放Look Up Table & Use Table

  46. Look Up table Mechanism • Look Up Table : 需要1000個10bit,一般用1000個2Bytes,所以佔2048Bytes • Use Table : 需要1024個1bit = 128Bytes,有用或Bad Block set to 1. For Search Free Block

  47. Look Up table Mechanism • Logical Address to Physical Address PS:另外整個Disk還有一個Table紀錄 Lookup Table Address in each Zone

  48. Outline • NAND Flash SPEC • NAND Flash Controller & Control Code • Look up Table Mechanism • NAND Flash Code Flow • FAT SPEC • FAT Code Flow • FILE Process

  49. Write Logical 寫入資料是利用Swap Block ,先將資料寫入Swap Block中,再將其與原先應 寫入的Block作對調(Look Up Table上的對調),由於是整個Block的互換故 需考慮下列的特殊情形: • First Block: • 起始於Page0:資料完整可直接Change • 起始非Page0:需將起始Page前的Page資料(沒有Write的部分)複製至 Swap Block,然後才Change • Last Block: • 寫至Last Page:資料完整可直接Change • 未寫至Last Page:需將後面的原本資料複製至Swap Block,然後才 Change