Update on GTK ASIC development

1. Update on GTK ASIC development presented by A. Kluge CERN/PH-ESE April 4, 2011

2. Outline • Introduction, strategy • ASIC architecture • Status of • Pixel matrix: Front-end, trim DACs, inPixel configuration • Transmission line, receiver, hitArbiter • TDC: delay line, charge pump, hit registers • Read-out & configuration master • Outlook A. Kluge

3. 45 x 40 pixel full matrix 45 45 45 45 45 40 Hit Arbiter Hit Arbiter Hit Arbiter Hit Arbiter Addr. Addr. Addr. Addr. 32 Hit Reg2 Hit Reg1 Hit Reg2 Hit Reg1 Hit Reg2 Hit Reg1 Hit Reg2 Hit Reg1 LVDS Ref CLK 320MHz DLL Digital processing serializer

4. A. Kluge

5. Data format • Nominal transmission: 2.4 Gbits/s, • High speed: 3.2 Gbits/s • All words: 48 bits (6 bytes) long • 8b10 encoded  bit stream 60 bits • data word • frame word • idle (komma) word: no hits available to transmit, 6 * comma character (ie. K28.5) • sync word: after reset and after each force_sync command (can be sent repetitive)for 4 * 106 cycles, 100 ms @ 2.4 Gbit/s, 6 * comma character (ie. K27.7) • link checking sequence, known pattern (ie. counter) sent upon request • Header contains frame counter every 6.4 µs • Data contains dynamic range up to 6.4 µs + 1 overroll counter bit

6. Data format-hit word normal mode (48 bit) • Status/data selector 1 bit • Leading coarse time 12 bit 1bit rollover indicator+2048(11bit)*3.125 ns=6.4 µs • Leading coarse time selector 1 bit • Leading fine time 5 bit 98 ps -> 3.125 ns • Trailing coarse time 5 bit 32*3.125 ns = 100 ns • Trailing fine time 5 bit 98 ps -> 3.125 ns • Trailing coarse time selector 1 bit • Address 7 bit (90 pixel groups) • Address-hit arbiter 5 bit • Address pileup 5 bit • Error bit (SEU or overflow) 1 bit___________________________________________________________________________________ • Total 48 bit

7. Data format-status words • Two words • status/data selector 2 (for each one word)*2 bit • 11  status word • 10  error word, FIFO overflow information • frame counter 28 bit 2**28*6.4 µs=1718 s • # of hits in previous frame 7 bit 2**22=4E6, hits per quarter chip = 130 Mhits/s /4* 6.4 µs = 208 512  7 bit • # of SEU in previous frame 6 bit 2**6=64, 64/6.4µs = 10E7 • Check sum 16 bit • spare info 37 bit___________________________________________________________________________________ • Total 96 bit = 2 * 48

8. idle word (48 bit) • 6 * Komma K28.5___________________________________________________________________________________ • Total 6 * 48 bit

9. sync word (48 bit) • 6 * Komma K27.7___________________________________________________________________________________ • Total 6 * 48 bit

10. I/O

11. Pixel matrix: Front-end, trim DACs, inPixel configuration A. Kluge

12. pixel matrix J. Kaplon A. Kluge

13. 2 column structure J. Kaplon A. Kluge

14. pixel cell Discriminator has been adapted for the threshold trim DAC5 bit inPixel trim DAC addedinPixel configuration addedinPixel configuration is based on serial chain of 4 columns controlled by EOC located master, TMR SEU protection scheme, along with single bit self correction possibility J. Kaplon & M. Noy A. Kluge

15. Transmission line receiver hitArbiter A. Kluge

16. Transmission line, receiver, hitArbiter • Transmission driver & line & receiver unchanged from prototype • hitArbiter (5 to 1 Mux maintaining time information) improved: • qualified with VHDL hit generator reflecting beam profile (1 GHz) • output: pixel address & 2 time stamps (hit) & OR pixel address & no time stamp (pileup) • efficiency center column, center pixel group, 1GHz beam: (hit+pileup info)/particles = 99.8% hit/particles = 99.1% A. Kluge

17. hitArbiter A. Kluge

18. TDC: delay line, charge pump, enocoder, fine hitRegisters • layout placed in 300 µm column • DLL code encoder added • delay line & output buffer scheme power consumption reduced to 19.7 mW per delay line • TDC expert design review • charge pump, fine hit registers layout unmodified • parallel read-out to hit registers added • startup state machine still need to be integrated • delay line output to hit registers qualified and buffered • bus structure to connect hitArbiter, TDC, hitRegisters implemented and qualified A. Kluge

19. TDC A. Kluge G. Aglieri

20. TDC A. Kluge G. Aglieri

21. TDC: delay line, charge pump, encoder, fine hitRegisters G. Aglieri A. Kluge

22. TDC: DLL & charge pump A. Kluge L. Perktold

23. Fine hit registers G. Aglieri A. Kluge

24. TDC: encoder G. Aglieri A. Kluge

25. Read-out & configuration master • Configuration master: • based on simple serial protocol • being designed in standard cell at the moment • Standard cell & custom cell read-out will be tackled after the afore mentioned blocks A. Kluge

26. Verifications • Single block verification (analog, digital) • Full matrix and automatic functional simulation (mixed mode, fully HDL based) • using hitGenerator as particle stimulus • using correct configuration data • SEU simulations A. Kluge

27. Outlook & Summary • Pixel matrix: Front-end, trim DACs, inPixel configuration • Transmission line, receiver, hitArbiter • TDC: delay line, charge pump, hit registers • Read-out • Chip assembly • Functional & tape-out simulations A. Kluge

28. A. Kluge

30. Implementation data transmission; 60bit/5IO • Multi Serial60bit: • 60 bits (8b10); 5 I/O pairs • FIFO read-frequency for 50% contingency on 132 Mhits/s  50 MHz / quarter chip * 60 bit /5 pairs (10 bits serializer)  3000 /5 = 600 MHz per LVDS pair • Input frequency comes from PLL or from outside, either 2.4 Gbit/s on pad or 480 MHz for all pads & synchronous logic • if synchronous logic works with 480 MHz only  480 MHz * 5 = 2400 Mbit/s  / 60  40 Mhits/s  (21 % (132 Mhits/s) +54 % (104 Mhit/s)) • Worst case • synchronous logic works with 320 MHz only  320 MHz * 5 = 1600 Mbit/s  / 60  26.7 Mhits/s  (-19 % (132 Mhits/s) +3 % (104 Mhit/s)) • synchronous logic works with 240 MHz only  240MHz * 5 = 1200 Mbit/s  / 60  20 Mhits/s  (-39 % (132 Mhits/s) -23 % (104 Mhit/s))