Precise Timing Adjustment for the ATLAS Level1 Endcap Muon Trigger System

1. Precise Timing Adjustment for the ATLAS Level1 Endcap Muon Trigger System Yu Suzuki (KEK) on behalf of the ATLAS Collaboration

2. Contents • Level-1 Endcap Muon Trigger System • Timing Adjustment • Signal timing • adjustment between channels • Clock phase • adjustment between clock and the bunch crossing • Summary TWEPP09 Yu Suzuki

3. LVL1 Muon Trigger System • TGC(1.05<η <2.4) • Thin Gap Chamber • 320k channels • RPC(η < 1.05) • Resistive Plate Chamber • 360k channels P(40MHz) P 25m 44m LVL1 muon trigger system • Toroidal Magnets (Barrel + Endcap) • 2-8T m • LVL1-Trigger • Second coordinate TWEPP09 Yu Suzuki

4. End cap Muon Trigger System (TGC) R-Z cross-section view of TGC (m) R TGC2 TGC3 12 TGC system TGC1 Synchronize signals with Bunch-crossing clock (BCID) Measure the transverse momentum (pT) with 3 station coincidence, every bunch crossing. Send muon candidates above pT=6GeV to the central trigger processor (CTP) 10 Front End Electronics (FE) 8 toroidal magnet μ 6 4 2 (m) 16 6 8 10 12 14 Z TWEPP09 Yu Suzuki

5. Timing adjustment of TGC signals FE μ ASD Latest signal TGC3 TOF + Cable delay TGC2 TGC1 T BC Clock (40MHz=25nsec) TWEPP09 Yu Suzuki

6. Intrinsic time jitter TGC intrinsic time jitteris comparable with bunch-crossing interval.  need to align the timing difference in channel to channel with nano-second level for BCID TGC intrinsic time jitter distribution measured by test beam 25nsec BC Clock Cent Prev Next TWEPP09 Yu Suzuki

7. Clock phase adjustment TGC intrinsic time jitteris comparable with bunch-crossing space.  need to align the timing difference in channel to channel with nano-second level for BCID need to adjust the clock phase on FE with real bunch crossing (clock phase scan) TGC intrinsic time jitter distribution measured by test beam 25nsec BC Clock (not adjusted) BC Clock (adjusted) Prev Cent Next Cent Prev Next Δ TWEPP09 Yu Suzuki

8. Functionalities of timing adjustment Time difference from TOF & cable length Signal Delay Phase difference between real bunch-crossing and the Clock on FEClock Delay • Clock Delay • 0.5 nsec/step • 64 steps • Signal Delay • 0.83 nsec/step • 32 steps TTC (Timing Trigger Control) TTCrx BCID Clock ASD TWEPP09 Yu Suzuki

9. Sources of Delay R-Z cross-section view TGC2 R (m) 12 TGC3 • TOF(time of flight) • 45 - 64 nsec TGC1 10 • Signal cable length 8 1.8 -12.5m (9- 63 nsec) (834types) toroidal magnet 6 4 . 2 (m) 16 6 8 10 12 14 Z TWEPP09 Yu Suzuki

10. Test Pulse Function • We use TestPulse function for timing adjustment. • TP Generator transmits TestPulse to ASD, when TP Trigger comes. TestPulse timing can be changed by preset delay. pulse gen Test Pulse TestPulse delay Test Pulse trigger • 0.83 nsec/step • 32 step TestPulse delay twisted pair cable TGC BCID Signal delay ASD LVDS • Using Test Pulse • We measure a propagation delay of cables. • We validate a signal timing for all TGCchannels. TWEPP09 Yu Suzuki

11. Measurementof propagation delay • We measured a propagation velocity in cables, and found 20 (cm/nsec). • Additional we have to consider the effect of the signal attenuations in the cables • preamp out length：3.5m length：42.0 m • preamp out the effect of the signal attenuation ΔDelay(nsec) ΔDelay=propagation delay －velocity*length • LVDS • LVDS Cable length(m) • We decide Signal Delay and TestPulse Delay with considered this effect. TWEPP09 Yu Suzuki

12. Timing validationby using Test Pulse Timing of cables nominal Calculate delay parameters from nominal cable length at cable production. Make Corrections to individual type of cables Make Corrections to individual cable signal entry type cable timing of All cables are aligned within 5nsec Signal timing(0.83nsec/BIN) TWEPP09 Yu Suzuki

13. Clock phase adjustment • LHC will start collisionin43/156bunches mode. We plan the clock phase scan in this stage. Expected structure in 43 bunch mode Zoom T Out of phase BC Clock (best phase) Best phase Prev Cent Next Next Next Cent Cent BC Clock (out of phase) Prev Cent Next BCID Prev=LHC filled bunch -1 Cent=LHC filled bunch • We would like to find the best clock phase with respect to Bunch Collision. Next=LHC filled bunch +1 TWEPP09 Yu Suzuki

14. Determination of best clock phase We will decide the best phase by using the ratio. Clock phase shift vs Ratio (simulation) 1000 events Best phase Cent Next Prev Best phase Next Cent BCID shift of clock phase(ns) Expected L1A rate @ L=1031(cm-2s-1) 500Hz TWEPP09 Yu Suzuki

15. Location of Delay circuits in TGC system TTCrx TTCrx TestPulse Trigger TTCvi Clock BCID CTP Clock BCID delay Sub-nano step BCID 1/2 clock step 1/2 nano step TWEPP09 Yu Suzuki

16. Module for phase scan VME Delay Module VME crate for TGC-TTC system • 4 inputs,4outputs • ECL Input/Output (AC/DC couple) • 0.5nsec/step 64steps TWEPP09 Yu Suzuki

17. SUMMARY Precise timing adjustment is essential for Level-1 muon trigger system. Signal delay parameters are calculated from TOF and the cable length and they are validated by using TestPulse. We have established the procedure of the clock phase adjustment, by using beam. We have developed a delay module for the purpose. We are ready for beam. TWEPP09 Yu Suzuki

18. Back Up TWEPP09 Yu Suzuki

19. Delay scan L1A signal timing delay delay T BC clock Read out read out bunch prev Cent Next T

20. Timing Parameter correction Correction for same cable Correction for each cable TWEPP09 Yu Suzuki

21. Timing chart BCID Delay Signal Delay Bunch Cross 64.6 81.2 Assumed BC 44.9 57.0 BCID Delay Signal Delay TGC1 TGC1 85.7 115.9 Variable delay BCID LVDS 49.5 62.9 TGC2 Variable delay BCID LVDS TGC2 Signal Delay 69.8 88.9 TGC3 50.9 63.9 Variable delay BCID LVDS TGC3 40MHz clk μ N-1 Bunch N Bunch N+1 Bunch TWEPP09 Yu Suzuki

22. accuracy of measurement Timing (1step=0.83nsec) Timing (1step=0.83nsec) Timing distribution expected from correction value timing residual between 2 mesurement • RMS=0.5step=0.4nsec Round off effect Test Pulse error RMS=0.6step=0.5nsec TWEPP09 Yu Suzuki

23. effect of Vth, HV value Simulation Blue:100mV Black:80mV Red:70mV Timing (1step=0.83nsec) The effect of Vth ,HV <1 nsec TWEPP09 Yu Suzuki