4 bit arithmatic and logic unit fairchild dm74ls181 l.
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4 BIT Arithmatic and Logic Unit (Fairchild DM74LS181). Kunjal Shah Radha Dharmana Rutu Pandya Vennela Patchala. Advisor: Dr. David, Parent December 5, 2005. Agenda. Abstract Introduction Why Simple Theory Back Ground information (Lit Review) Design Flow Project (Experimental) Details

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4 bit arithmatic and logic unit fairchild dm74ls181

4 BIT Arithmatic and Logic Unit(Fairchild DM74LS181)

Kunjal Shah

Radha Dharmana

Rutu Pandya

Vennela Patchala.

Advisor: Dr. David, Parent

December 5, 2005

agenda
Agenda
  • Abstract
  • Introduction
    • Why
    • Simple Theory
    • Back Ground information (Lit Review)
  • Design Flow
  • Project (Experimental) Details
  • Results
  • Cost Analysis
  • Lessons Learned
  • Acknowledgement
abstract
Abstract

Specifications of ALU

  • Load : 25 fF
  • 16 arithmathic functions
  • 16 logical functions
  • Propagation delay : 5ns
  • Clock frequency : 200 MHz
  • Power requirement : 17 mW
  • Occupied Area : 373 x373um
introduction
Introduction

Why?

  • The Arithmatic and Logic Unit is a building block of several industrial circuits.
  • Design consists of different kinds of Arithmatic operations like Ripple carry adder, subtractor, Transfer data..

Logical operations like AND, OR, XOR, INV.

  • How the ALU is designed and how it works is essential for designing advanced circuits.
logical operations
Logical Operations

F = (A XOR B)

F = (AB) '

arithmetic operations
Arithmetic Operations

F = AB'- 1

F = AB- 1

transient response
Transient Response

A=0, B=1, M=1, S=E, F0 =1, F1=F2 = F3 = 0, F =A+B

cost analysis
Cost Analysis
  • Time spent on each phase of the project
    • Verifying logic 1 week
    • Logic reduction 1 week
    • Transistor sizing 1 week
    • Layout of individual blocks 2weeks
    • Integration of blocks 3 days
    • post extracted timing 1 day
lessons learned
Lessons Learned
  • The circuit can be used as a building block for 16/32-bit ALU.
  • Same metal should not be used in both horizontal and vertical direction.
acknowledgement
Acknowledgement
  • Thanks to Cadence Design Systems for the VLSI lab
  • Thanks to Professor David W. Parent for his guidance.