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Computer Arithmatic. Pradondet Nilagupta Spring 2005 (original notes from Prof. J. Kelly Flanagan). Computer Arithmetic. This lecture will introduce basic number representations and introduce basic integer and floating point arithmetic. Arithmetic. operation. a. ALU. 32. result. 32. b.

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## Computer Arithmatic

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**Computer Arithmatic**Pradondet Nilagupta Spring 2005 (original notes from Prof. J. Kelly Flanagan) 204521 Digital System Architecture**Computer Arithmetic**• This lecture will introduce basic number representations and introduce basic integer and floating point arithmetic. 204521 Digital System Architecture**Arithmetic**operation a ALU 32 result 32 b 32 • Where we've studied so far: • Boolean algebra and basic logic circuits • Abstractions: Instruction Set Assembly Language and Machine Language • What's up ahead: • Implementing the Architecture • So we understand instructions better 204521 Digital System Architecture**Number Representation**• Any number can be represented in any base by the simple sum of each digit's value, positional notation: d * basei • The value 1011 (binary) equals 1 * 23 + 0 * 22 + 1 * 21 + 1 * 20 = 11 (decimal). 204521 Digital System Architecture**Number Representation**• as a 32 bit number this would be represented as follows: 0000 0000 0000 0000 0000 0000 0000 1011 • The most significant bit (MSB) is on the left and the least significant bit (LSB) is on the right. In the number above, the LSB is called bit 0 and the MSB is called bit 31. 204521 Digital System Architecture**Range of Values**• With 32 bits it is possible to have unsigned numbers that range from 0 to 232 - 1 = 4,294,967,295. • This is quite reasonable for address calculations of present machines, but future machines will surely have more than 232 memory locations. • In addition to more memory it is highly useful to be able to represent negative as well as positive integers and numbers smaller and larger then those possible with this format. 204521 Digital System Architecture**MIPS**maxint minint • 32 bit signed numbers:0000 0000 0000 0000 0000 0000 0000 0000two = 0ten0000 0000 0000 0000 0000 0000 0000 0001two = + 1ten0000 0000 0000 0000 0000 0000 0000 0010two = + 2ten...0111 1111 1111 1111 1111 1111 1111 1110two = + 2,147,483,646ten0111 1111 1111 1111 1111 1111 1111 1111two = + 2,147,483,647ten1000 0000 0000 0000 0000 0000 0000 0000two = – 2,147,483,648ten1000 0000 0000 0000 0000 0000 0000 0001two = – 2,147,483,647ten1000 0000 0000 0000 0000 0000 0000 0010two = – 2,147,483,646ten...1111 1111 1111 1111 1111 1111 1111 1101two = – 3ten1111 1111 1111 1111 1111 1111 1111 1110two = – 2ten1111 1111 1111 1111 1111 1111 1111 1111two = – 1ten 204521 Digital System Architecture**Signed Integers**• Since in the binary number system we have an even number of unique representations for a given number of bits we have two choices: 1. Have a balanced system with the same number of negative and positive values, but what about zero? If we represent zero we have an odd number of values to represent. This can be done by allowing zero to be represented by two different bit patterns. 204521 Digital System Architecture**Signed Integers**2. Have an unbalanced system where zero has one representation, but there is either an extra positive or negative value. • We would like a balanced system, but this would require two different representations for the value zero. • This evil (having two zeros) is better to avoid and not worth the benefits of having a balanced system. Consequently, an unbalanced system has been nearly universally adopted. 204521 Digital System Architecture**One's Complement**• How can we represent negative and positive numbers in the binary system? • The 1's complement number system using 32 bits has a range from -(2^31 -1) to +(2^31 - 1). • Zero can be represented as either positive or negative. The two forms of zero are represented by 0000 0000 0000 0000 0000 0000 0000 0000 (all zeros) or 1111 1111 1111 1111 1111 1111 1111 1111 (all ones). 204521 Digital System Architecture**One's Complement**• A negative number is formed by representing its magnitude in normal, positive binary format and then inverting each bit. • 8-bit examples: 1111 1110 = -1 1111 1111 = -0 0000 0000 = +0 0000 0001 = +1 • Having two forms of zero is a problem, but arithmetic is simple. 204521 Digital System Architecture**Two's Complement**• The 2's complement number system using 32 bits has a range from -2^31 to 2^31 - 1. • Zero has only one representation: all zeros, but there is one extra negative value. • Negative numbers always have the MSB set to 1 -- thus making sign detection extremely simple. • Converting 2's complement numbers to signed decimal is extremely simple. 204521 Digital System Architecture**Example 2’s complement**Convert 1011 1010 to signed decimal. 1 * -27 + 0 * 26 + 1 * 25 + 1 * 24 + 1 * 23 + 0 * 22 + 1 * 21 + 0 * 20 = -128 + 0 + 32 + 16 + 8 + 0 + 2 + 0 = -70. • This approach is not feasible in hardware due to speed considerations. 204521 Digital System Architecture**Two's Complement Shortcuts**• Negation in two's complement is accomplished by inverting each bit of the number and then adding one to the result. • Example: Convert -70 (decimal) to two's complement binary. |-70| = 70 = 0100 0110 (binary) ~ 0100 0110 = 1011 1001 (where ~ denotes bit inversion) 1011 1001 + 1 = 1011 1010 = -70 (2's comp). 204521 Digital System Architecture**Sign Extension**• To add a 16-bit value to a 32-bit value, the 16-bit value must first be sign extended. The two numbers are right aligned and the sign bit of the shorter number is replicated to the left until the two numbers are equal in length. 204521 Digital System Architecture**Example Sign Extension**0000 0000 0000 0000 0000 0000 0000 1011 + 1011 1010 we must sign extend the second number and then add: 0000 0000 0000 0000 0000 0000 0000 1011 + 1111 1111 1111 1111 1111 1111 1011 1011 ------------------------------------------------------------- 1 1111 1111 1111 1111 1111 1111 1100 0101 • The extra bit on the left is simply discarded, leaving us with 1111 1111 1111 1111 1111 1111 1100 0101 for our answer. 204521 Digital System Architecture**Possible Number Representations**• Sign Magnitude: One's Complement Two's Complement 000 = +0 000 = +0 000 = +0 001 = +1 001 = +1 001 = +1 010 = +2 010 = +2 010 = +2 011 = +3 011 = +3 011 = +3 100 = -0 100 = -3 100 = -4 101 = -1 101 = -2 101 = -3 110 = -2 110 = -1 110 = -2 111 = -3 111 = -0 111 = -1 204521 Digital System Architecture**Integer Addition**• Straight forward approach consists of adding each bit together from right to left and propagating the carry from one bit to the next. Perform the operation 7 + 6 0111 + 0110 = 1101 204521 Digital System Architecture**Integer Addition**Add the numbers 2,147,483,647 + 2 0111 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0010 This is known as overflow Overflow can be handled in several ways • An exception or interrupt can be asserted • A bit in a status register can be set • It can be completely ignored 204521 Digital System Architecture**Integer Subtraction**• Straight forward approach consists of negating one term and performing integer addition. Perform the operation 7 - 6 0111 - 0110 = 0001 Perform the operation 6 - 7 0110 - 0111 = 1111 204521 Digital System Architecture**Integer Subtraction**Add the numbers -2,147,483,647 - 2 1000 0000 0000 0000 0000 0000 0000 0001 1111 1111 1111 1111 1111 1111 1111 1110 This is also overflow Overflow can be handled in several ways • An exception or interrupt can be asserted • A bit in a status register can be set • It can be completely ignored 204521 Digital System Architecture**Integer Overflow**• Overflow can occur whenever the sum of two N bit numbers cannot be represented by another N bit number. • Unsigned numbers must be treated differently than signed numbers. • Unsigned numbers are usually used for address calculations and it is convenient to ignore overflow. • In many architectures this is accomplished by having arithmetic instructions that ignore the overflow condition. 204521 Digital System Architecture**Detecting Overflow**• No overflow when adding a positive and a negative number • No overflow when signs are the same for subtraction • Overflow occurs when the value affects the sign: • overflow when adding two positives yields a negative • or, adding two negatives gives a positive • or, subtract a negative from a positive and get a negative • or, subtract a positive from a negative and get a positive • Consider the operations A + B, and A – B • Can overflow occur if B is 0 ? • Can overflow occur if A is 0 ? 204521 Digital System Architecture**Effects of Overflow**• Most processors hardware automatically generates an exception (interrupt) • Control jumps to predefined address for exception • Interrupted address is saved for possible resumption • Details will be studied in a later chapter • Don't always want to detect overflow — new MIPS instructions: addu, addiu, subu — Here, “u” stands for “un-overflowed”. note: addiu still sign-extends! note: sltu, sltiu for unsigned comparisons 204521 Digital System Architecture**Designing an ALU**• Not easy to decide the “best” way to build something • Don't want too many inputs to a single gate • Don’t want to have to go through too many gates • for our purposes, ease of comprehension is important • Let's look at a 1-bit ALU for addition:How could we build a 1-bit ALU for add, and, and or? • How could we build a 32-bit ALU? cout = a b + a cin + b cin sum = a xor b xor cin 204521 Digital System Architecture**Building a 32 bit ALU**Each box is a 1bit ALU 204521 Digital System Architecture**What about subtraction (a – b) ?**• Two's complement approach: just negate b and add. • How do we negate? • A very clever solution: 1-bit ALU w/ negation 204521 Digital System Architecture**Tailoring the ALU to the MIPS**• Need to support the set-on-less-than instruction (slt) • remember: slt is an arithmetic instruction • produces a 1 if rs < rt and 0 otherwise • use subtraction: (a-b) < 0 implies a < b • Need to support test for equality (beq $t5, $t6, $t7) • use subtraction: (a-b) = 0 implies a = b 204521 Digital System Architecture**Supporting Set Less Than (slt)**• Can we figure out the idea? 204521 Digital System Architecture**Test for equality**• Notice control lines:000 = and001 = or010 = add110 = subtract111 = slt • Note: zero is a 1 when the result is zero! 204521 Digital System Architecture**Conclusion**• We can build an ALU to support the MIPS instruction set • key idea: use multiplexor to select the output we want • we can efficiently perform subtraction using two’s complement • we can replicate a 1-bit ALU to produce a 32-bit ALU • Important points about hardware • all of the gates are always working • the speed of a gate is affected by the number of inputs to the gate • the speed of a circuit is affected by the number of gates in series (on the “critical path” or the “deepest level of logic”) • Our primary focus: comprehension, however, • Clever changes to organization can improve performance (similar to using better algorithms in software) • we’ll look at two examples for addition and multiplication 204521 Digital System Architecture**Problem: ripple carry adder is slow**• Is a 32-bit ALU as fast as a 1-bit ALU? • Is there more than one way to do addition? • two extremes: ripple carry and sum-of-products Can you see the ripple? How could you get rid of it? c1 = b0c0 + a0c0 +a0b0 c2 = b1c1 + a1c1 +a1b1 c2 = c3 = b2c2 + a2c2 +a2b2 c3 = c4 = b3c3 + a3c3 +a3b3 c4 = Not feasible! Why? 204521 Digital System Architecture**Carry-look-ahead adder**• An approach in-between our two extremes • Motivation: • If we didn't know the value of carry-in, what could we do? • When would we always generate a carry? gi = ai bi • When would we propagate the carry? pi = ai + bi • Did we get rid of the ripple? c1 = g0 + p0c0 c2 = g1 + p1c1 c2 = c3 = g2 + p2c2 c3 = c4 = g3 + p3c3 c4 =Feasible! Why? 204521 Digital System Architecture**Use principle to build bigger adders**• Can’t build a 16 bit adder this way... (too big) • Could use ripple carry of 4-bit CLA adders • Better: use the CLA principle again! 204521 Digital System Architecture**Longhand Multiplication**• Multiply 1000 * 1001 (either decimal or binary will work!) Multiplicand 1000 Multiplier 1001 1000 0000 0000 1000 ------- Product 1001000 204521 Digital System Architecture**Longhand Multiplication**• The first number is the multiplicand and the second the multiplier. • The result is larger than either the multiplicand or the multiplier. If the size of the multiplicand is N bits and the size of the multiplier is M bits then the result is M+N bits long. 204521 Digital System Architecture**Simple Multiplication Algorithm**• The Multiplicand is stored in a 64 bit register and the Multiplier is stored in a 32 bit register while the product register is 64 bits long and initialized to zero. • Test bit 0 of the multiplier If this bit is 0 Continue If this bit is 1 Add the multiplicand to the product and store back in the product register Shift the multiplicand register left 1 bit Shift the multiplier register right 1 bit If this is the 32nd iteration END else continue 204521 Digital System Architecture**MULTIPLY HARDWARE Version 1**Shift Left 64-bit Multiplicand Shift Right 32-bit Multiplier 64-bit ALU Write 64-bit Product Control • 64-bit Multiplicand reg, 64-bit ALU, 64-bit Product reg, 32-bit multiplier reg 204521 Digital System Architecture**Multiply Algorithm Version 1**Start Multiplier0 = 1 TestMultiplier0 Multiplier0 = 0 1. Add multiplicand to product & place the result in Product register 2. Shift the Multiplicand register left 1 bit. 3. Shift the Multiplier register right 1 bit. 32nd repetition? No: < 32 repetitions Yes: 32 repetitions Done 204521 Digital System Architecture**Try It Yourself, V1**• 4x4 bit Multiply, Version 1 • Show each step for 5 x 11 = 55 MultiplierMultiplicandProduct Operation 0101 0000 1011 0000 0000 initial load 204521 Digital System Architecture**Solution, V1**• 5 x 11 = 55MultiplierMultiplicandProduct Operation 0101 0000 1011 0000 0000 initial load 0101 0000 0011 0000 1011 add 0010 0001 0110 0000 1011 shift 0010 0001 0110 0000 1011 no add 0001 0010 1100 0000 1011 shift 0001 0010 1100 0011 0111 add 0000 0101 1000 0011 0111 shift 0000 0101 1000 0011 0111 no add 0000 1011 0000 0011 0111 shift 204521 Digital System Architecture**Observations on Multiply Version 1**• 1 clock per cycle --> 32 x 3 = 100 clocks per multiply • Ratio of multiply frequency to add is 5:1 to 100:1 • But remember Amdahl’s Law! • 1/2 bits in multiplicand always 0 • 64-bit adder is wasted • 0’s inserted in right side of multiplicand as shifted • least significant bits of product never changed once formed • Instead of shifting multiplicand to left, shift product to right? 204521 Digital System Architecture**A Better Multiplier**• In the previous algorithm half of the bits in the multiplicand register are zero and contain no needed information. This algorithm requires only a 32 bit ALU and multiplicand register If multiplier bit 0 = 0 Continue if multiplier bit 0 = 1 Add the multiplicand to the left half of the product register and store the result in the left half Shift the product and multiplier registers right 1 bit. If this is the 32nd iteration END otherwise continue 204521 Digital System Architecture**MULTIPLY HARDWARE Version 2**• 32-bit Multiplicand reg, 32 -bit ALU, 64-bit Product reg, 32-bit Multiplier reg 32-bit Multiplicand 32-bit Multiplier Shift Right 32-bit ALU Shift Right 64-bit Product Control Write 204521 Digital System Architecture**Multiply Algorithm Version 2**Start Multiplier0 = 1 TestMultiplier0 Multiplier0 = 0 1. Add multiplicand to the left half of product & place the result in the left half of Product register 2. Shift the Product register right 1 bit. 3. Shift the Multiplier register right 1 bit. 32nd repetition? No: < 32 repetitions Yes: 32 repetitions Done 204521 Digital System Architecture**4x4 bit Multiply, Version 2**Show each step for 5 x 11 = 55 MultiplierMultiplicandProduct Operation 0101 1011 0000 0000 initial load Try It Yourself, V2 204521 Digital System Architecture**Solution, V2**• 5 x 11 = 55MultiplierMultiplicandProduct Operation 0101 1011 0000 0000 initial load 0101 1011 1011 0000 add 0010 1011 0101 1000shift 0010 1011 0101 1000 no add 0001 1011 0010 1100shift 0001 1011 1101 1100 add 0000 1011 0110 1100shift 0000 1011 0110 1100 no add 0000 1011 0011 0111 shift 204521 Digital System Architecture**Observations on Multiply Version 2**• Right half of product register wastes space that exactly matches size of multiplier • So put multiplier in right half of product register ? 204521 Digital System Architecture**Another Multiplier**• In the previous algorithm the lower bits of the product register are wasted and could be used to store the multiplier. If product bit 0 = 0 Continue if product bit 0 = 1 Add the multiplicand to the left half of the product register and store the result in the left half Shift the product register right 1 bit. If this is the 32nd iteration END otherwise continue 204521 Digital System Architecture

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