1 / 62

Revolutionary Approaches in Sub-lithographic Semiconductor Computing

Explore the advancement in computing systems beyond lithographic limits using bottom-up nanowire growth and molecular engineering. Learn about sub-nm-scale structures and innovative memory logic designs.

sguevara
Download Presentation

Revolutionary Approaches in Sub-lithographic Semiconductor Computing

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson, Charles Lieber, Patrick Lincoln, and John Savage

  2. Approaching the Bottom • In 1959, Feynman pointed out we had • “plenty of room at the bottom” • Suggested: • wires ~ 10-100 atoms diameter • circuits ~ few thousands angstroms ~ few hundred nm

  3. Approaching the Bottom • Today we have 90nm Si processes • bottom is not so far away • Si Atom • 0.5nm lattice spacing • 90nm ~ 180 atoms diameter wire

  4. Exciting Advances in Science • Beginning to be able to manipulate things at the “bottom” -- atomic scale engineering • designer/synthetic molecules • carbon nanotubes • silicon nanowires • self-assembled mono layers • designer DNA

  5. Question • Can we build interesting computing systems without lithographic patterning? • Primary interest: below lithographic limits

  6. Why do we care? • Lithographic limitations • Already stressing PSM • …xrays, electron projection… • Lithographic costs Source: Kahng/ITRS2001

  7. Today’s Talk Bottom up tour: from Si atoms to Computing • Nanowire • growth • devices • assembly • differentiation • coding • Nanoscale memories from nanowires • Logic: nanoPLAs • Interconnected nanoPLAs • Analysis

  8. SiNWGrowth • Atomic structure determines feature size • Self-same crystal structure constrains growth • Catalyst defines/constrains structure

  9. SiNW Growth

  10. SiNW Growth

  11. Building Blocks

  12. Semiconducting Nanowires • Few nm’s in diameter (e.g. 3nm) • Diameter controlled by seed catalyst • Can be microns long • Control electrical properties via doping • Materials in environment during growth • Control thresholds for conduction From: Cui…Lieber APL v78n15p2214

  13. Radial Modulation Doping • Can also control doping profile radially • To atomic precision • Using time Lauhon et. al. Nature 420 p57

  14. Diode and FET Junctions Devices Doped nanowires give: Huang…Lieber Science 294 p1313 Cui…Lieber Science 291 p851

  15. Transfer aligned NWs to patterned substrate Transfer second layer at right angle + Langmuir-Blodgett (LB) transfer • Can transfer tight-packed, aligned SiNWs onto surface • Maybe grow sacrificial outer radius, close pack, and etch away to control spacing Whang, Nano Letters 2003 (to appear)

  16. Homogeneous Crossbar • Gives us homogeneous NW crossbar • Undifferentiated wires • All do the same thing

  17. Control NW Dopant • Can define a dopant profile along the length of a wire • Control lengths by timed growth • Change impurities present in the environment as a function of time Gudiksen et. al. Nature 415 p617 Björk et. al. Nanoletters 2 p87

  18. Control NW Dopant • Can define a dopant profile along the length of a wire • Control lengths by timed growth • Change impurities present in the environment as a function of time • Get a SiNW banded with differentiated conduction/gate-able regions Gudskien et. al. Nature 415 p617 Björk et. al. Nanoletters 2 p87

  19. Enables: Differentiated Wires • Can engineer wires • Portions of wire always conduct) • Portions controllable

  20. Coded Wires • By selectively making bit-regions on wires either highly or lightly doped • Can give the wire an address

  21. Unique Set of Codes • If we can assemble a set of wires with unique codes • We have an address decoder

  22. Unique Set of Codes • If we can assemble a set of wires with unique codes • We have an address decoder • Apply a code • k-hot code • Unique code selects a single wire

  23. Statistical Coding • Unique Code set achievable with statistical assembly (random mixing) • Consider: • Large code space (106 codes) • Large number of wires of each type (1012) • Small array (10 wires) chosen at random • Likelihood all 10 unique? • Very high! (99.995%) DeHon et. al. IEEE TNANO v2n3p165

  24. Codespace: How Large? • How large does code space really need to be? • Addressing N wires • With code space 100N2 • Has over 99% probability of all wires being unique • For logarithmic decoder: • Need a little over 2 bits of sparse code

  25. Electrostatic Switches Molecular Switches Collier et. al. Science 289 p1172 Ruekes et. al. Science 289 p04 Switches / Memories

  26. Common Switchpoint Properties • Fit in space of NW crossing • Hysteretic I-V curves • Set/reset with large differential voltage across crosspoint • Operate at lower voltage

  27. Memories

  28. Basis for Sublithographic Memory

  29. Precharge all lines low

  30. Drive Column Read Address

  31. Pulls Single Column Line High

  32. On xpoint allow to pull Row lines to be pulled high Assume here: only the two points shown are “on”. i.e. column has 0 1 0 0 1 0

  33. All Rows Disabled Read output not driven; sees 0

  34. Select Read Row 1010 Read output now pulled high; sees 1

  35. Select Read Row 1100 Read output not driven; sees 0

  36. …on to Logic…

  37. Diode Logic • Arise directly from touching NW/NTs • Passive logic • Non-restoring • Non-volatile Programmable crosspoints

  38. Use to build Programmable OR-plane • But.. • OR is not universal • Diode logic is non-restoring  no gain, cannot cascade

  39. PMOS-like Restoring FET Logic • Use FET connections to build restoring gates • Static load • Like NMOS (PMOS) • Maybe precharge

  40. Ideal vs. Stochastic Restore

  41. Simple Nanowire-Based PLA NOR-NOR = AND-OR PLA Logic

  42. Defect Tolerant All components (PLA, routing, memory) interchangeable; Have M-choose-N property Allows local programming around faults

  43. 60 OR-term PLA Useable 131 raw row wires Defects Misalign 171 raw inverting wires Defects Statistical population 60M sq. nm. (2 planes) Simple PLA Area 90nm support lithography; 10nm nanowire pitch

  44. Crosspoint Defects • Crosspoint junctions may be nonprogrammable • E.g. HPs first 8x8 had 85% programmable crosspoints • Tolerate by matching nanowire junction programmability with pterm needs • Less than ~10% overhead for crosspoint defect rates up to 20% Naeimi/DeHon, FPT2004

  45. Interconnected nanoPLAs

  46. Tile into Arrays

  47. Manhattan Routing

  48. Manhattan Routing

  49. Tile into Arrays

  50. Know NOR gates are universal Selective inversion Interconnect structure for arbitrary routing Can compute any logic function Can combine with nanomemories Complete Substrate for Computing

More Related