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Structural and Behavioral Design Style Registers, Counters, and Testbenches. Resources. Sundar Rajan, Essential VHDL: RTL Synthesis Done Right Chapter 4, Registers and Latches Chapter 5, Counters and Simple Arithmetic Functions
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ECE 449 – Computer Design Lab
ECE 449 – Computer Design Lab
ECE 449 – Computer Design Lab
Major instructions
ECE 449 – Computer Design Lab
Major instructions
ECE 449 – Computer Design Lab
in1
nand_out
in2
in1
Component NAND2 Instantiated Four Time
ECE 449 – Computer Design Lab
Major instructions
ECE 449 – Computer Design Lab
xor_tmp(0)
xor_tmp(1)
xor_tmp(2)
xor_tmp(3)
xor_tmp(4)
xor_tmp(5)
xor_tmp(6)
xor_tmp(7)
ECE 449 – Computer Design Lab
Architecture with for-generate
architecture STRUCTURE of PARITY is
component XOR2
port(
A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC
);
end component;
signal xor_tmp: std_logic_vector (0 to 7);
begin
xor_tmp(0) <= parity_in(0);
G: for i in 0 to 6 generate
C: XOR2 port map(A=>xor_tmp(i),
B=>parity_in(i+1),
Y=>xor_tmp(i+1));
end generate;
parity_out <= xor_tmp(7);
end STRUCTURE;
ECE 449 – Computer Design Lab
Major instructions
ECE 449 – Computer Design Lab
entity PARITY is
generic(N: positive);
port(
parity_in : in STD_LOGIC_VECTOR(N-1 downto 0);
parity_out : out STD_LOGIC
);
end PARITY;
ECE 449 – Computer Design Lab
architecture STRUCTURE of PARITY is
component XOR2
port(
A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC
);
end component;
signal xor_tmp: std_logic_vector (0 to N-1);
begin
xor_tmp(0) <= parity_in(0);
G: for i in 0 to N-2 generate
C: XOR2 port map(A=>xor_tmp(i),
B=>parity_in(i+1),
Y=>xor_tmp(i+1));
end generate;
parity_out <= xor_tmp(N-1);
end STRUCTURE;
ECE 449 – Computer Design Lab
ECE 449 – Computer Design Lab
Major instructions
Sequential statements
General
Registers, counters, shift registers, etc.
State machines
Testbenches
ECE 449 – Computer Design Lab
OPTIONAL
[label:] process[(sensitivity list)]
[declaration part]
begin
statement part
end process;
ECE 449 – Computer Design Lab
The Keyword PROCESS
TESTING: process
begin
TEST_VECTOR<=“00”;
wait for 10 ns;
TEST_VECTOR<=“01”;
wait for 10 ns;
TEST_VECTOR<=“10”;
wait for 10 ns;
TEST_VECTOR<=“11”;
wait for 10 ns;
end process;
ECE 449 – Computer Design Lab
Whenever there is an event on any of the signals in the sensitivity list, the process fires.
Every time the process fires, it will run in its entirety.
WAIT statements NOT ALLOWED in a processes with SENSITIVITY LIST.
label: process (sensitivity list)
declaration part
begin
statement part
end process;
PROCESS with a SENSITIVITY LISTECE 449 – Computer Design Lab
ECE 449 – Computer Design Lab
All signals which appear on the right of signal assignment statement (<=) or in logic expressions are inputse.g. w, a, b, c
All signals which appear in the sensitivity list are inputs e.g. clk
Note that not all inputs need to be in the sensitivity list
Component Equivalent of a Processclk
y
w
priority
a
z
b
c
priority: PROCESS (clk)
BEGIN
IF w(3) = '1' THEN
y <= "11" ;
ELSIF w(2) = '1' THEN
y <= "10" ;
ELSIF w(1) = c THEN
y <= a and b;
ELSE
z <= "00" ;
END IF ;
END PROCESS ;
ECE 449 – Computer Design Lab
ECE 449 – Computer Design Lab
D
Clock
D latch
Truth table
Graphical symbol
Q(t+1)
Clock
D
Q(t)
–
0
0
1
0
1
1
1
Timing diagram
t
t
t
t
1
2
3
4
Clock
D
Q
Time
ECE 449 – Computer Design Lab
D
Clock
D flip-flop
Truth table
Graphical symbol
Q(t+1)
Clk
D
0
0
1
1
–
Q(t)
0
Q(t)
1
–
Timing diagram
t
t
t
t
1
2
3
4
Clock
D
Q
Time
ECE 449 – Computer Design Lab
D
Clock
D latch
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY latch IS
PORT ( D, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC) ;
END latch ;
ARCHITECTURE Behavior OF latch IS
BEGIN
PROCESS ( D, Clock )
BEGIN
IF Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior;
ECE 449 – Computer Design Lab
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY flipflop IS
PORT ( D, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC) ;
END flipflop ;
ARCHITECTURE Behavior_1 OF flipflop IS
BEGIN
PROCESS ( Clock )
BEGIN
IF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior_1 ;
Q
D
Clock
ECE 449 – Computer Design Lab
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY flipflop IS
PORT ( D, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC) ;
END flipflop ;
ARCHITECTURE Behavior_2 OF flipflop IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ;
Q <= D ;
END PROCESS ;
END Behavior_2 ;
Q
D
Clock
ECE 449 – Computer Design Lab
D flip-flop with asynchronous reset
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY flipflop IS
PORT ( D, Resetn, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC) ;
END flipflop ;
ARCHITECTURE Behavior OF flipflop IS
BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN
Q <= '0' ;
ELSIF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
Q
D
Clock
Resetn
ECE 449 – Computer Design Lab
D flip-flop with synchronous reset
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY flipflop IS
PORT ( D, Resetn, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC) ;
END flipflop ;
ARCHITECTURE Behavior OF flipflop IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ;
IF Resetn = '0' THEN
Q <= '0' ;
ELSE
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
Q
D
Clock
Resetn
ECE 449 – Computer Design Lab
8
Resetn
D
Q
Clock
reg8
8-bit register with asynchronous reset
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY reg8 IS
PORT ( D : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;
Resetn, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ;
END reg8 ;
ARCHITECTURE Behavior OF reg8 IS
BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN
Q <= "00000000" ;
ELSIF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;`
ECE 449 – Computer Design Lab
N
Resetn
D
Q
Clock
regn
N-bit register with asynchronous reset
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY regn IS
GENERIC ( N : INTEGER := 16 ) ;
PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Resetn, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END regn ;
ARCHITECTURE Behavior OF regn IS
BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN
Q <= (OTHERS => '0') ;
ELSIF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
ECE 449 – Computer Design Lab
N
N-bit register with enable
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY regn IS
GENERIC ( N : INTEGER := 8 ) ;
PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Enable, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END regn ;
ARCHITECTURE Behavior OF regn IS
BEGIN
PROCESS (Clock)
BEGIN
IF (Clock'EVENT AND Clock = '1' ) THEN
IF Enable = '1' THEN
Q <= D ;
END IF ;
END IF;
END PROCESS ;
END Behavior ;
Enable
Q
D
Clock
regn
ECE 449 – Computer Design Lab
ECE 449 – Computer Design Lab
Clear
Q
upcount
Clock
2-bit up-counter with synchronous reset
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
ENTITY upcount IS
PORT ( Clear, Clock : IN STD_LOGIC ;
Q : BUFFER STD_LOGIC_VECTOR(1 DOWNTO 0) ) ;
END upcount ;
ARCHITECTURE Behavior OF upcount IS
BEGIN
upcount: PROCESS ( Clock )
BEGIN
IF (Clock'EVENT AND Clock = '1') THEN
IF Clear = '1' THEN
Q <= "00" ;
ELSE
Q <= Q + “01” ;
END IF ;
END IF;
END PROCESS;
END Behavior ;
ECE 449 – Computer Design Lab
4
Q
Clock
upcount
Resetn
4-bit up-counter with asynchronous reset (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
ENTITY upcount IS
PORT ( Clock, Resetn, Enable : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)) ;
END upcount ;
ECE 449 – Computer Design Lab
4
Q
Clock
upcount
Resetn
4-bit up-counter with asynchronous reset (2)
ARCHITECTURE Behavior OF upcount IS
SIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0) ;
BEGIN
PROCESS ( Clock, Resetn )
BEGIN
IF Resetn = '0' THEN
Count <= "0000" ;
ELSIF (Clock'EVENT AND Clock = '1') THEN
IF Enable = '1' THEN
Count <= Count + 1 ;
END IF ;
END IF ;
END PROCESS ;
Q <= Count ;
END Behavior ;
ECE 449 – Computer Design Lab
ECE 449 – Computer Design Lab
D(0)
D
D
D
D
Q
Q
Q
Q
Load
D(3)
D(1)
D(2)
Sin
Clock
Enable
Q(3)
Q(2)
Q(1)
Q(0)
ECE 449 – Computer Design Lab
4
Enable
D
Q
Load
Sin
shift4
Clock
4-bit shift register with parallel load (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY shift4 IS
PORT ( D : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
Enable : IN STD_LOGIC ;
Load : IN STD_LOGIC ;
Sin : IN STD_LOGIC ;
Clock : IN STD_LOGIC ;
Q : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END shift4 ;
ECE 449 – Computer Design Lab
4
Enable
D
Q
Load
Sin
shift4
Clock
4-bit shift register with parallel load (2)
ARCHITECTURE Behavior_1 OF shift4 IS
BEGIN
PROCESS (Clock)
BEGIN
IF Clock'EVENT AND Clock = '1' THEN
IF Load = '1' THEN
Q <= D ;
ELSIF Enable = ‘1’ THEN
Q(0) <= Q(1) ;
Q(1) <= Q(2);
Q(2) <= Q(3) ;
Q(3) <= Sin;
END IF ;
END IF ;
END PROCESS ;
END Behavior_1 ;
ECE 449 – Computer Design Lab
4
Enable
D
Q
Load
Sin
shift4
Clock
4-bit shift register with parallel load (3)
ARCHITECTURE Behavior_2 OF shift4 IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ;
IF Load = '1' THEN
Q <= D ;
ELSIF Enable = ‘1’ THEN
Q(3) <= Sin;
Q(2) <= Q(3) ;
Q(1) <= Q(2);
Q(0) <= Q(1) ;
END IF ;
END PROCESS ;
END Behavior_2 ;
Incorrect!!!
ECE 449 – Computer Design Lab
N
N
D
Q
Load
Sin
shiftn
Clock
N-bit shift register with parallel load (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY shiftn IS
GENERIC ( N : INTEGER := 8 ) ;
PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Enable : IN STD_LOGIC ;
Load : IN STD_LOGIC ;
Sin : IN STD_LOGIC ;
Clock : IN STD_LOGIC ;
Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END shiftn ;
ECE 449 – Computer Design Lab
N
N
D
Q
Load
Sin
shiftn
Clock
N-bit shift register with parallel load (2)
ARCHITECTURE Behavior OF shiftn IS
BEGIN
PROCESS (Clock)
BEGIN
IF (Clock'EVENT AND Clock = '1' ) THEN
IF Load = '1' THEN
Q <= D ;
ELSIF Enable = ‘1’ THEN
Genbits: FOR i IN 0 TO N-2 LOOP
Q(i) <= Q(i+1) ;
END LOOP ;
Q(N-1) <= Sin ;
END IF;
END IF ;
END PROCESS ;
END Behavior ;
ECE 449 – Computer Design Lab
Design Under Test (DUT)
Rule of Thumb: Usually ports from DUT entities are declared as signals within testbench
Testbench Environment
Stimuli All DUT Inputs
Sources of
Input
Stimuli
Simulated Outputs
ECE 449 – Computer Design Lab
Entity TB is
--TB entity has no ports
End TB;
Architecture arch_TB of TB is
--Local signals and constants
component TestComp --All Design Under Test component declarations
port ( );
endcomponent;
-----------------------------------------------------
for DUT:TestComp useentitywork.TestComp(archName)--Specify entity/arch pair
-- (OPTIONAL)
begin
testSequence: Process
--Main test process
end process;
DUT:TestComp portmap( --Port map all the DUTs
);
End arch_TB;
ECE 449 – Computer Design Lab
When the process fires, the first statement after the keyword BEGIN is executed.
The execution of statements continues sequentially till the last statement in the process.
After execution of the last statement, the control is again passed to the beginning of the process.
TESTING: process
begin
TEST_VECTOR<=“00”;
wait for 10 ns;
TEST_VECTOR<=“01”;
wait for 10 ns;
TEST_VECTOR<=“10”;
wait for 10 ns;
TEST_VECTOR<=“11”;
wait for 10 ns;
end process TESTING;
Execution of statements in a PROCESSOrder of execution
Program control is passed to the first statement after BEGIN
ECE 449 – Computer Design Lab
This will cause the PROCESS to suspend indefinitely when the WAIT statement is executed.
This form of WAIT can be used in a process included in a testbench when all possible combinations of inputs have been tested or a non-periodical signal has to be generated.
TESTING: process
begin
TEST_VECTOR<=“00”;
wait for 10 ns;
TEST_VECTOR<=“01”;
wait for 10 ns;
TEST_VECTOR<=“10”;
wait for 10 ns;
TEST_VECTOR<=“11”;
wait;
end process TESTING;
PROCESS with a WAIT StatementOrder of execution
Program execution stops here
ECE 449 – Computer Design Lab
0
0
1
1
2
2
3
3
Wait for: waveform will keep repeating itself forever
…
Wait: waveform will keep its state after the last wait instruction.
…
ECE 449 – Computer Design Lab
[label:] process[(sensitivity list)]
[declaration part]
begin
statement part
end process;
ECE 449 – Computer Design Lab
ECE 449 – Computer Design Lab
ifboolean expression then
statements
elsif boolean expression then
statements
else boolean expression then
statements
end if;
ECE 449 – Computer Design Lab
SELECTOR: process
begin
WAIT UNTIL Clock'EVENT AND Clock = '1' ;
IF Sel = “00” THEN
f <= x1;
ELSIF Sel = “10” THEN
f <= x2;
ELSE
f <= x3;
END IF;
end process;
ECE 449 – Computer Design Lab
casecondition is
when choice_1 =>
statements
when choice_2 =>
statements
when choice_n =>
statements
end case;
ECE 449 – Computer Design Lab
FSM_transitions: PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN y <= S1 ;
ELSIF (Clock'EVENT AND Clock = '1') THEN
CASE y IS
WHEN S1 =>
IF s = '0' THEN y <= S1; ELSE y <= S2 ; END IF ;
WHEN S2 =>
IF z = '0' THEN y <= S2 ; ELSE y <= S3 ; END IF ;
WHEN S3 =>
IF s = '1' THEN y <= S3 ; ELSE y <= S1 ; END IF ;
END CASE ;
END IF ;
END PROCESS ;
ECE 449 – Computer Design Lab
fori in range loop
statements
end loop;
ECE 449 – Computer Design Lab
TEST_DATA_GENERATOR: process
begin
TEST_AB<="00";
TEST_SEL<="00";
for I in 0 to 3 loop
for J in 0 to 3 loop
wait for 10 ns;
TEST_AB<=TEST_AB+"01";
end loop;
TEST_SEL<=TEST_SEL+"01";
end loop;
end process;
ECE 449 – Computer Design Lab
Concurrent Statements
architecture ARCHITECTURE_NAME of ENTITY_NAME is
begin
Concurrent statements:
end ARCHITECTURE_NAME;
ECE 449 – Computer Design Lab
VHDL description
Block diagram
architecture MLU_DATAFLOW of MLU is
signal A1:STD_LOGIC;
signal B1:STD_LOGIC;
signal Y1:STD_LOGIC;
signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC;
begin
A1<=A when (NEG_A='0') else
not A;
B1<=B when (NEG_B='0') else
not B;
Y<=Y1 when (NEG_Y='0') else
not Y1;
MUX_0<=A1 and B1;
MUX_1<=A1 or B1;
MUX_2<=A1 xor B1;
MUX_3<=A1 xnor B1;
with (L1 & L0) select
Y1<=MUX_0 when "00",
MUX_1 when "01",
MUX_2 when "10",
MUX_3 when others;
end MLU_DATAFLOW;
ECE 449 – Computer Design Lab
ECE 449 – Computer Design Lab
