Lessons from last lab:

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Lessons from last lab:. Many had the “# skipping” problem Most assumed there was something wrong with their code How does one check their code? SIMULATE!! What if the simulation shows that your code works just fine? It must be the hardware!

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Presentation Transcript
Lessons from last lab:
• Many had the “# skipping” problem
• Most assumed there was something wrong with their code
• How does one check their code?
• SIMULATE!!
• What if the simulation shows that your code works just fine?
• It must be the hardware!
• First principle of electrical engineering: ALWAYS BLAME THE EQUIPMENT
“Debounce”

outp

D Q

clk

D Q

clk

D Q

clk

delay1

delay2

delay3

inp

cclk

This circuit can be used to debounce a pushbotton input signal (inp). The frequency of the input clock, cclk, must be low enough that the switch bouncing is over before three clock periods. You might be able to use the slow_clk that you used for the displays refresh in displays.v

PROBLEM 1

module reg12 (q, d, clk);

output [11:0] q;

input [11:0] d;

input clk ;

reg [11:0] q;

always @(posedge clk)

q <= d;

endmodule

PROBLEM 2

module max_pipeline (max, a, b, c, clk);

output [13:0] max;

input [13:0] a, b, c;

input clk;

wire [13:0] max_a_b, max_a_b_c;

reg [13:0] saved_max_a_b, saved_c;

assign max_a_b = a > b ? a : b;

always @(posedge clk) // Pipeline register 1

begin

saved_max_a_b <= max_a_b;

saved_c <= c;

end

assign max_a_b_c = saved_max_a_b > saved_c ? saved_max_a_b : saved_c;

always @(posedge clk) // Pipeline register 2

max <= max_a_b_c;

endmodule

PROBLEM 3

module peak_detector (data_out, data_in, data_en, clk, reset);

output [9:0] data_out;

input [9:0] data_in;

input data_en, clk, reset;

reg [9:0] data_out;

always @(posedge clk)

if (reset) data_out <= 0;

else if (update_peak) data_out <= data_in;

endmodule

PROBLEM 4

We can derive the control signal by decoding the count value 4 (00100), 20 (10100) and 24 (11000). Since the binary codes for 4 and 20 are the same in all but the most-significant bit, we can decode them jointly (X0100). The circuit is:

PROB 4 continued

module decoded_counter (ctrl, clk );

output ctrl;

input clk;

reg [4:0] count_value;

always @(posedge clk)

count_value <= count_value + 1;

assign ctrl = count_value == 5'b11000 || count_value[3:0] == 4'b0100;

endmodule